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authorMatthew McClintock <msm@freescale.com>2012-08-13 10:00:40 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 10:24:17 -0500
commit02ea538ce9fa8325f7d15c69cf87c950c5fe1f57 (patch)
tree15066f5b6df8b756f4fbb264ccf32522d8e27dbf
parent8c454047fe9c08a51410dca01b945cdcecb18b7e (diff)
downloadu-boot-02ea538ce9fa8325f7d15c69cf87c950c5fe1f57.tar.gz
nand_spl: p1023rds: wait before enabling DDR controller
We have a requirement to wait a period of time before enabling the DDR controller Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
-rw-r--r--nand_spl/board/freescale/p1023rds/Makefile6
-rw-r--r--nand_spl/board/freescale/p1023rds/nand_boot.c19
2 files changed, 20 insertions, 5 deletions
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index 168e868641..da435213fc 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
+ ../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+$(obj)../common.c:
+ @rm -f $(obj)../common.c
+ ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 0065c876de..6ab1f50378 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -25,6 +25,10 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
@@ -53,20 +57,27 @@ void sdram_init(void)
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+ /* Set, but do not enable the memory */
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
}
void board_init_f(ulong bootflag)
{
- u32 plat_ratio, bus_clk;
+ u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* Initialize the DDR3 */