Merge branch '2020-07-29-add-brcm-ns3-support'

- Add initial Broadcom NS3 SoC support.

33 files changed, 2304 insertions, 44 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index eac3832fa2..889a73f15f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -969,6 +969,21 @@ S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/
 
+TARGET_BCMNS3
+M:	Bharat Gooty <bharat.gooty@broadcom.com>
+M:	Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcmns3/
+F:	doc/README.bcmns3
+F:	configs/bcm_ns3_defconfig
+F:	include/configs/bcm_ns3.h
+F:	include/dt-bindings/memory/bcm-ns3-mc.h
+F:	arch/arm/Kconfig
+F:	arch/arm/dts/ns3-board.dts
+F:	arch/arm/dts/ns3.dtsi
+F:	arch/arm/cpu/armv8/bcmns3
+F:	arch/arm/include/asm/arch-bcmns3/
+
 TDA19988 HDMI ENCODER
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Maintained
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ded8cfee09..3e11ddfa9b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
 
 config GIC_V3_ITS
 	bool "ARM GICV3 ITS"
+	select REGMAP
+	select SYSCON
 	help
 	  ARM GICV3 Interrupt translation service (ITS).
 	  Basic support for programming locality specific peripheral
@@ -732,6 +734,15 @@ config TARGET_BCMNS2
 	  ARMv8 Cortex-A57 processors targeting a broad range of networking
 	  applications.
 
+config TARGET_BCMNS3
+	bool "Support Broadcom NS3"
+	select ARM64
+	select BOARD_LATE_INIT
+	help
+	  Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
+	  ARMv8 Cortex-A72 processors targeting a broad range of networking
+	  applications.
+
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
 	select DM
@@ -1916,6 +1927,7 @@ source "board/broadcom/bcm968580xref/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
 source "board/broadcom/bcmns2/Kconfig"
+source "board/broadcom/bcmns3/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
 source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 2e48df0eb9..7e33a183d5 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
 obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
+obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
new file mode 100644
index 0000000000..a35e29d11a
--- /dev/null
+++ b/arch/arm/cpu/armv8/bcmns3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Broadcom.
+
+obj-y	+= lowlevel.o
diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
new file mode 100644
index 0000000000..bf1a17ab03
--- /dev/null
+++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+hnf_pstate_poll:
+	/* x0 has the desired status, return 0 for success, 1 for timeout
+	 * clobber x1, x2, x3, x4, x6, x7
+	 */
+	mov	x1, x0
+	mov	x7, #0			/* flag for timeout */
+	mrs	x3, cntpct_el0		/* read timer */
+	mov	w0, #600
+	mov	w6, #1000
+	mul	w0, w0, w6
+	add	x3, x3, x0		/* timeout after 100 microseconds */
+	mov	x0, #0x18
+	movk	x0, #0x6120, lsl #16	/* HNF0_PSTATE_STATUS */
+	mov	w6, #4			/* HN-F node count */
+1:
+	ldr	x2, [x0]
+	cmp	x2, x1			/* check status */
+	b.eq	2f
+	mrs	x4, cntpct_el0
+	cmp	x4, x3
+	b.ls	1b
+	mov	x7, #1			/* timeout */
+	b	3f
+2:
+	add	x0, x0, #0x10000	/* move to next node */
+	subs	w6, w6, #1
+	cbnz	w6, 1b
+3:
+	mov	x0, x7
+	ret
+
+hnf_set_pstate:
+	/* x0 has the desired state, clobber x1, x2, x6 */
+	mov	x1, x0
+	/* power state to SFONLY */
+	mov	w6, #4			/* HN-F node count */
+	mov	x0, #0x10
+	movk x0, #0x6120, lsl #16		/* HNF0_PSTATE_REQ */
+1:	/* set pstate to sfonly */
+	ldr	x2, [x0]
+	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
+	orr	x2, x2, x1
+	str	x2, [x0]
+	add	x0, x0, #0x10000	/* move to next node */
+	subs	w6, w6, #1
+	cbnz	w6, 1b
+
+	ret
+
+ENTRY(__asm_flush_l3_dcache)
+	/*
+	 * Return status in x0
+	 *    success 0
+	 *    timeout 1 for setting SFONLY, 2 for FAM, 3 for both
+	 */
+	mov	x29, lr
+	mov	x8, #0
+
+	dsb	sy
+	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
+	bl	hnf_set_pstate
+
+	mov	x0, #0x4		/* SFONLY status */
+	bl	hnf_pstate_poll
+	cbz	x0, 1f
+	mov	x8, #1			/* timeout */
+1:
+	dsb	sy
+	mov	x0, #0x3		/* HNFPSTAT_FAM */
+	bl	hnf_set_pstate
+
+	mov	x0, #0xc		/* FAM status */
+	bl	hnf_pstate_poll
+	cbz	x0, 1f
+	add	x8, x8, #0x2
+1:
+	mov	x0, x8
+	mov	lr, x29
+	ret
+ENDPROC(__asm_flush_l3_dcache)
+
+ENTRY(save_boot_params)
+/*
+ * void set_boot_params(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3)
+ */
+	adr	x4, bl33_info
+	str	x0, [x4]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0cd8e92e81..fde893e8c9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -41,37 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE		ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
-				PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
-	u32 phandle;
-	int err;
-	struct fdt_memory gic_rd_tables;
-
-	gic_rd_tables.start = base;
-	gic_rd_tables.end = base + size - 1;
-	err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
-					 &phandle);
-	if (err < 0)
-		debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
-	return err;
-}
-
 int ls_gic_rd_tables_init(void *blob)
 {
-	u64 gic_lpi_base;
 	int ret;
 
-	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
-	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
-	if (ret)
-		return ret;
-
-	ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	ret = gic_lpi_tables_init();
 	if (ret)
 		debug("%s: failed to init gic-lpi-tables\n", __func__);
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index caa7756c5d..153698a6b8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -930,6 +930,8 @@ dtb-$(CONFIG_ARCH_BCM68360) += \
 dtb-$(CONFIG_ARCH_BCM6858) += \
 	bcm968580xref.dtb
 
+dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
+
 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
new file mode 100644
index 0000000000..4e0966a132
--- /dev/null
+++ b/arch/arm/dts/ns3-board.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier:      GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/memory/bcm-ns3-mc.h>
+
+/*
+ * Single mem reserve region which includes the following:
+ * Components name	Start Addr	Size
+ * ------------------------------------------------
+ * GIC LPI tables	0x8ad7_0000	0x0009_0000
+ * Nitro FW		0x8ae0_0000	0x0020_0000
+ * Nitro Crash dump	0x8b00_0000	0x0200_0000
+ * OPTEE OS		0x8d00_0000	0x0200_0000
+ * BL31 services	0x8f00_0000	0x0010_0000
+ * Tmon			0x8f10_0000	0x0000_1000
+ * LPM/reserved		0x8f10_1000	0x0000_1000
+ * ATF to Bl33 info	0x8f10_2000	0x0000_1000
+ * ATF error logs	0x8f10_3000	0x0001_0000
+ * Error log parser	0x8f11_3000	0x0010_0000
+ */
+
+/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
+
+/* CRMU page tables */
+/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
+
+#include "ns3.dtsi"
+
+/ {
+	model = "NS3 model";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi
new file mode 100644
index 0000000000..09098aac3a
--- /dev/null
+++ b/arch/arm/dts/ns3.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier:      GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "brcm,ns3";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>,
+			<0x8 0x80000000 0x1 0x80000000>;
+	};
+
+	hsls {
+		compatible = "simple-bus";
+		dma-ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x68900000 0x17700000>;
+
+		uart1: uart@110000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x00110000 0x1000>;
+			reg-shift = <2>;
+			clock-frequency = <25000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-bcmns3/bl33_info.h b/arch/arm/include/asm/arch-bcmns3/bl33_info.h
new file mode 100644
index 0000000000..bbc95b0186
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmns3/bl33_info.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#ifndef BL33_INFO_H
+#define BL33_INFO_H
+#include <asm/io.h>
+
+/* Increase version number each time this file is modified */
+#define BL33_INFO_VERSION	1
+
+struct chip_info {
+	unsigned int chip_id;
+	unsigned int rev_id;
+};
+
+struct bl33_info {
+	unsigned int version;
+	struct chip_info chip;
+};
+
+extern struct bl33_info *bl33_info;
+
+#endif
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
 #define GIC_REDISTRIBUTOR_OFFSET 0x20000
 
 #ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
 #else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
 {
 	return 0;
 }
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 7715a01706..7dc87afb83 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -2,7 +2,8 @@
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
 	!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
 	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
-	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
+	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
+	!defined(CONFIG_TARGET_BCMNS3)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..a1657e3853 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,9 @@
  * Copyright 2019 Broadcom.
  */
 #include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
 #include <asm/gic.h>
 #include <asm/gic-v3.h>
 #include <asm/io.h>
@@ -15,23 +18,104 @@ static u32 lpi_id_bits;
 #define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
 #define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
 
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS	8
+
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
+ */
+struct gic_v3_its_priv {
+	ulong gicd_base;
+	ulong gicr_base;
+	ulong lpi_base;
+	u32 num_redist;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+	struct udevice *dev;
+	fdt_addr_t addr;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_IRQ,
+					  DM_GET_DRIVER(arm_gic_v3_its), &dev);
+	if (ret) {
+		pr_err("%s: failed to get %s irq device\n", __func__,
+		       DM_GET_DRIVER(arm_gic_v3_its)->name);
+		return ret;
+	}
+
+	addr = dev_read_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE) {
+		pr_err("%s: failed to get GICD address\n", __func__);
+		return -EINVAL;
+	}
+	priv->gicd_base = addr;
+
+	addr = dev_read_addr_index(dev, 1);
+	if (addr == FDT_ADDR_T_NONE) {
+		pr_err("%s: failed to get GICR address\n", __func__);
+		return -EINVAL;
+	}
+	priv->gicr_base = addr;
+
+	return 0;
+}
+
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+	struct regmap *regmap;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+					  DM_GET_DRIVER(gic_lpi_syscon), &dev);
+	if (ret) {
+		pr_err("%s: failed to get %s syscon device\n", __func__,
+		       DM_GET_DRIVER(gic_lpi_syscon)->name);
+		return ret;
+	}
+
+	regmap = syscon_get_regmap(dev);
+	if (!regmap) {
+		pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+		       DM_GET_DRIVER(gic_lpi_syscon)->name);
+		return -ENODEV;
+	}
+	priv->lpi_base = regmap->ranges[0].start;
+
+	priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
+						MAX_GIC_REDISTRIBUTORS);
+
+	return 0;
+}
+
 /*
  * Program the GIC LPI configuration tables for all
  * the re-distributors and enable the LPI table
- * base: Configuration table address
- * num_redist: number of redistributors
  */
-int gic_lpi_tables_init(u64 base, u32 num_redist)
+int gic_lpi_tables_init(void)
 {
+	struct gic_v3_its_priv priv;
 	u32 gicd_typer;
 	u64 val;
 	u64 tmp;
 	int i;
 	u64 redist_lpi_base;
-	u64 pend_base = GICR_BASE + GICR_PENDBASER;
+	u64 pend_base;
 
-	gicd_typer = readl(GICD_BASE + GICD_TYPER);
+	if (gic_v3_its_get_gic_addr(&priv))
+		return -EINVAL;
+
+	if (gic_v3_its_get_gic_lpi_addr(&priv))
+		return -EINVAL;
 
+	gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
 	/* GIC support for Locality specific peripheral interrupts (LPI's) */
 	if (!(gicd_typer & GICD_TYPER_LPIS)) {
 		pr_err("GIC implementation does not support LPI's\n");
@@ -43,10 +127,10 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
 	 * Once the LPI table is enabled, can not program the
 	 * LPI configuration tables again, unless the GIC is reset.
 	 */
-	for (i = 0; i < num_redist; i++) {
+	for (i = 0; i < priv.num_redist; i++) {
 		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
 
-		if ((readl((uintptr_t)(GICR_BASE + offset))) &
+		if ((readl((uintptr_t)(priv.gicr_base + offset))) &
 		    GICR_CTLR_ENABLE_LPIS) {
 			pr_err("Re-Distributor %d LPI is already enabled\n",
 			       i);
@@ -59,25 +143,27 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
 			    ITS_MAX_LPI_NRBITS);
 
 	/* Set PropBase */
-	val = (base |
+	val = (priv.lpi_base |
 	       GICR_PROPBASER_INNERSHAREABLE |
 	       GICR_PROPBASER_RAWAWB |
 	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
 
-	writeq(val, (GICR_BASE + GICR_PROPBASER));
-	tmp = readl(GICR_BASE + GICR_PROPBASER);
+	writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+	tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
 			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
 				GICR_PROPBASER_CACHEABILITY_MASK);
 			val |= GICR_PROPBASER_NC;
-			writeq(val, (GICR_BASE + GICR_PROPBASER));
+			writeq(val,
+			       (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
 		}
 	}
 
-	redist_lpi_base = base + LPI_PROPBASE_SZ;
+	redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
 
-	for (i = 0; i < num_redist; i++) {
+	pend_base = priv.gicr_base + GICR_PENDBASER;
+	for (i = 0; i < priv.num_redist; i++) {
 		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
 
 		val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
@@ -94,9 +180,31 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
 		}
 
 		/* Enable LPI for the redistributor */
-		writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+		writel(GICR_CTLR_ENABLE_LPIS,
+		       (uintptr_t)(priv.gicr_base + offset));
 	}
 
 	return 0;
 }
 
+static const struct udevice_id gic_v3_its_ids[] = {
+	{ .compatible = "arm,gic-v3" },
+	{}
+};
+
+U_BOOT_DRIVER(arm_gic_v3_its) = {
+	.name		= "gic-v3",
+	.id		= UCLASS_IRQ,
+	.of_match	= gic_v3_its_ids,
+};
+
+static const struct udevice_id gic_lpi_syscon_ids[] = {
+	{ .compatible = "gic-lpi-base" },
+	{}
+};
+
+U_BOOT_DRIVER(gic_lpi_syscon) = {
+	.name		= "gic-lpi-base",
+	.id		= UCLASS_SYSCON,
+	.of_match	= gic_lpi_syscon_ids,
+};
diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig
new file mode 100644
index 0000000000..8ce21f980d
--- /dev/null
+++ b/board/broadcom/bcmns3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS3
+
+config SYS_BOARD
+	default "bcmns3"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "bcmns3"
+
+config SYS_CONFIG_NAME
+	default "bcm_ns3"
+
+endif
diff --git a/board/broadcom/bcmns3/Makefile b/board/broadcom/bcmns3/Makefile
new file mode 100644
index 0000000000..3404260148
--- /dev/null
+++ b/board/broadcom/bcmns3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Broadcom.
+
+obj-y	:= ns3.o
diff --git a/board/broadcom/bcmns3/fit/keys/dev.crt b/board/broadcom/bcmns3/fit/keys/dev.crt
new file mode 100644
index 0000000000..75b75db95c
--- /dev/null
+++ b/board/broadcom/bcmns3/fit/keys/dev.crt
@@ -0,0 +1,21 @@
+-----BEGIN CERTIFICATE-----
+MIIDXTCCAkWgAwIBAgIJAJgq/5aiJttEMA0GCSqGSIb3DQEBCwUAMEUxCzAJBgNV
+BAYTAkFVMRMwEQYDVQQIDApTb21lLVN0YXRlMSEwHwYDVQQKDBhJbnRlcm5ldCBX
+aWRnaXRzIFB0eSBMdGQwHhcNMTgwOTE5MDkzMzEwWhcNMTgxMDE5MDkzMzEwWjBF
+MQswCQYDVQQGEwJBVTETMBEGA1UECAwKU29tZS1TdGF0ZTEhMB8GA1UECgwYSW50
+ZXJuZXQgV2lkZ2l0cyBQdHkgTHRkMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIB
+CgKCAQEAzeMQ92YqrejtMCfxjDyHvDW34ATozXSlWsudR+AyCSuJVAIoHEenVh+/
+PuT0+/EMiwsUnLXYBeOsIXDW3k3eHgm88ccb+0g9J6mlHqMaN0tXP+Ua2GFEk2Wv
+5Bj5QynorOPoaWL/ecWus2Bvkmyt2pvIpaTjmkUKZ9al3z8WyS6wFlFitXyOWFcK
+7Xkl43cOHxYAfbny5loWYDCgpkV+dgYZOoCEmL+Y9HfrQ+uBKGducpzNKeQjX9bn
+UT9cleCtHZx0uY4wSGNgfmUMy7oUyVZhFpmjlcfjcfNFcBcoVF6StluoL6v1KRbH
+4xJDD/UCn2Uk0S6Zpd7TRc26faOtfwIDAQABo1AwTjAdBgNVHQ4EFgQUZk/KKaWG
+p4BtksPdQ8FLzWL/gAIwHwYDVR0jBBgwFoAUZk/KKaWGp4BtksPdQ8FLzWL/gAIw
+DAYDVR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAPNveTvOC2bw91cUN1e+B
+95qFp2Xd5XGiV35F10dT3VN/Iv2dzHlThq7xaJGkA53lHIXgLUUfnDTHJmoluw+t
+UCpG8OWCxM0FbT8ZnXR4SmHK8k4yb7iZa7iu+Ey5B6F3247gJpEl+1iYxus0lqQW
+E9dTwMf1YP9Jdf+dRoLKAAI0n5J1PMuseQkGdlRBNUcEg+kXqBSz5hq0xkuPRtey
+GiAvpg3G93ft84Q4ov7IjAhJkY7whm6WktisU8mFPru3e9EouxjVtAvu6s9gQThm
+pvn6hSL2/3gEOP3v9yBsH6//SOgNdVBGZIdX+HkvD8NZLftbIrDaeL/IfKUm/zXB
+zA==
+-----END CERTIFICATE-----
diff --git a/board/broadcom/bcmns3/fit/keys/dev.key b/board/broadcom/bcmns3/fit/keys/dev.key
new file mode 100644
index 0000000000..55b7033e9f
--- /dev/null
+++ b/board/broadcom/bcmns3/fit/keys/dev.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDN4xD3Ziqt6O0w
+J/GMPIe8NbfgBOjNdKVay51H4DIJK4lUAigcR6dWH78+5PT78QyLCxSctdgF46wh
+cNbeTd4eCbzxxxv7SD0nqaUeoxo3S1c/5RrYYUSTZa/kGPlDKeis4+hpYv95xa6z
+YG+SbK3am8ilpOOaRQpn1qXfPxbJLrAWUWK1fI5YVwrteSXjdw4fFgB9ufLmWhZg
+MKCmRX52Bhk6gISYv5j0d+tD64EoZ25ynM0p5CNf1udRP1yV4K0dnHS5jjBIY2B+
+ZQzLuhTJVmEWmaOVx+Nx80VwFyhUXpK2W6gvq/UpFsfjEkMP9QKfZSTRLpml3tNF
+zbp9o61/AgMBAAECggEBAJ/TZClZk0ob5nyalWVS29/cJ5hs1zgfE/nu1HKmdNEv
+jdS8M9z4Nsuhq3msjQ1Da4RInsCkXUT9H3N6QCKkeggBcT6TXYJs6qRuijLFVKWW
+A+4i8PsGTxDJQIimZmGgF/KWnaWp5z7lmZ+//fzCBxgMFO+Zl+H7NH+1XmB2fj6/
+bfgnxLbiIqq/2oVJfdjA1Zs2ie3SE5U2hPNiE6TIajFS0PxUOGrojsSQ8z+gfqs3
+hyqo9msAqNQciT79vyXp+3HsxZo9rq5Tk5OtCEfgu0GED/d4/FHbDrZT3TorVYXr
+Z3dADxvnnJfBdlQIMetCy/X8z2vKRRXaoWpqg1aiFVECgYEA7Ap5D4nvOie2NXgI
+gMPzuYtpH4uF/cZMLGxTKZ3NG4RH6oVUdd4whETXfzBJdnJbIXDTphoHxjUhpGh8
+Ga+U1iqjp9c6Nd8ueVp/c5T1bD8/2RG0QM4iWgPbZDKtj1MqRg7vwAfpJ3kOIc/5
+bKJ4jAopNJMChL6vAZ9+ShPsRqkCgYEA30vbj6K7/giclJnyWkluQTqS8X/XjdAf
+F5PkCBHGJnYxkDSzWPq7O5E1wYqTAou1U6nNNoUvZZdpRvo39NSrMCaagQ7GE+xA
+j/h7tinD/lPlvoW9N4f4ddqWzsmf7I8OGZtP4IwVi9Pms+zPtrQ7TvuPT4UHTH2E
+eE1hlJtic+cCgYEA6oKdNGr+WvEJfqX7DLOiej2f+89LGI7jL1+QYFB/b09FhCNj
+fpd57G/ZCmyXEC8di2PlY6mI/8vZ2NZWNc7UONO0NRUIqG1MZxUae2MLUrikXq3Q
+QHKMfpJGbo5LEZK29VPxrwAtDSKgf8d5MA1bZwbRWYKVhf1NMnebqU2R+cECgYEA
+kOTKXhP85MR1xj928XtAnfcCLs8D8jOgWU5P46SU7ZQ4aRipYA2ivO5m8WWYK0i4
+qsc+MCiQLt3nJHVtJeNyCdai3yfVBEyDQGi+7d+AHGIYbF6f/46tfNwQi7JtobTa
+M2eCl3SO7qLbytjZl/avnXrC7Zimuc2gzed4cFO7uPUCgYAo66MLtRWLdHqPDTaa
+WhSQZkdKfZxlWNP6XIpBgHnYDIQGZddrjv+zZVFRxLCduh1v8xybbSDKwRkGuXVb
+eTQHP2Nc5XsOopCSsDP0v0dUxaOu14C0jJJG2E+EhJsWJ2Eua7o40LEIX2WY7N7f
+UqR3bLO5Qh/1OOwJj5WbpzkMwA==
+-----END PRIVATE KEY-----
diff --git a/board/broadcom/bcmns3/fit/multi.its b/board/broadcom/bcmns3/fit/multi.its
new file mode 100644
index 0000000000..a0ff4bc908
--- /dev/null
+++ b/board/broadcom/bcmns3/fit/multi.its
@@ -0,0 +1,59 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Various kernels, ramdisks and FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel {
+			description = "Linux kernel Image";
+			data = /incbin/("./Image");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "none";
+			load = <0x80080000>;
+			entry = <0x80080000>;
+			hash-1 {
+				algo = "sha1";
+			};
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+
+		fdt-ns3 {
+			description = "FDT Blob";
+			data = /incbin/("./dt-blob.bin");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+	};
+
+	configurations {
+		default = "config-ns3";
+		config-ns3 {
+			description = "FIT1 configuration";
+			kernel = "kernel";
+			fdt = "fdt-ns3";
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+				sign-images = "fdt", "kernel";
+			};
+		};
+	};
+};
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
new file mode 100644
index 0000000000..0357cd0e32
--- /dev/null
+++ b/board/broadcom/bcmns3/ns3.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gic-v3.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-bcmns3/bl33_info.h>
+#include <dt-bindings/memory/bcm-ns3-mc.h>
+
+/* Default reset-level = 3 and strap-val = 0 */
+#define L3_RESET	30
+
+#define BANK_OFFSET(bank)      ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
+
+/*
+ * ns3_dram_bank - DDR bank details
+ *
+ * @start: DDR bank start address
+ * @len: DDR bank length
+ */
+struct ns3_dram_bank {
+	u64 start[BCM_NS3_MAX_NR_BANKS];
+	u64 len[BCM_NS3_MAX_NR_BANKS];
+};
+
+/*
+ * ns3_dram_hdr - DDR header info
+ *
+ * @sig: DDR info signature
+ * @bank: DDR bank details
+ */
+struct ns3_dram_hdr {
+	u32 sig;
+	struct ns3_dram_bank bank;
+};
+
+static struct mm_region ns3_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = BCM_NS3_MEM_START,
+		.phys = BCM_NS3_MEM_START,
+		.size = BCM_NS3_MEM_LEN,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = BCM_NS3_BANK_1_MEM_START,
+		.phys = BCM_NS3_BANK_1_MEM_START,
+		.size = BCM_NS3_BANK_1_MEM_LEN,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = ns3_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Force the bl33_info to the data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+struct bl33_info *bl33_info __section(".data");
+
+/*
+ * Run modulo 256 checksum calculation and return the calculated checksum
+ */
+static u8 checksum_calc(u8 *p, unsigned int len)
+{
+	unsigned int i;
+	u8 chksum = 0;
+
+	for (i = 0; i < len; i++)
+		chksum += p[i];
+
+	return chksum;
+}
+
+/*
+ * This function parses the memory layout information from a reserved area in
+ * DDR, and then fix up the FDT before passing it to Linux.
+ *
+ * In the case of error, do nothing and the default memory layout in DT will
+ * be used
+ */
+static int mem_info_parse_fixup(void *fdt)
+{
+	struct ns3_dram_hdr hdr;
+	u32 *p32, i, nr_banks;
+	u64 *p64;
+
+	/* validate signature */
+	p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
+	hdr.sig = *p32;
+	if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
+		printf("DDR info signature 0x%x invalid\n", hdr.sig);
+		return -EINVAL;
+	}
+
+	/* run checksum test to validate data  */
+	if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
+		printf("Checksum on DDR info failed\n");
+		return -EINVAL;
+	}
+
+	/* parse information for each bank */
+	nr_banks = 0;
+	for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
+		/* skip banks with a length of zero */
+		p64 = (u64 *)BANK_OFFSET(i);
+		if (*(p64 + 1) == 0)
+			continue;
+
+		hdr.bank.start[i] = *p64;
+		hdr.bank.len[i] = *(p64 + 1);
+
+		printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
+		       hdr.bank.start[i] + hdr.bank.len[i] - 1);
+		nr_banks++;
+	}
+
+	if (!nr_banks) {
+		printf("No DDR banks detected\n");
+		return -ENOMEM;
+	}
+
+	return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
+				      nr_banks);
+}
+
+int board_init(void)
+{
+	/* Setup memory using "memory" node from DTB */
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+	fdtdec_setup_memory_banksize();
+
+	if (bl33_info->version != BL33_INFO_VERSION)
+		printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
+	 * So that relocation happens with in the last 16MB memory.
+	 */
+	gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
+	gd->ram_size = (unsigned long)SZ_16M;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+	gd->bd->bi_dram[0].size = SZ_16M;
+
+	return 0;
+}
+
+/* Limit RAM used by U-Boot to the DDR first bank End region */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return BCM_NS3_MEM_END;
+}
+
+void reset_cpu(ulong level)
+{
+	u32 reset_level, strap_val;
+
+	/* Default reset type is L3 reset */
+	if (!level) {
+		/*
+		 * Encoding: U-Boot reset command expects decimal argument,
+		 * Boot strap val: Bits[3:0]
+		 * reset level: Bits[7:4]
+		 */
+		strap_val = L3_RESET % 10;
+		level = L3_RESET / 10;
+		reset_level = level % 10;
+		psci_system_reset2(reset_level, strap_val);
+	} else {
+		/* U-Boot cmd "reset" with any arg will trigger L1 reset */
+		psci_system_reset();
+	}
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	gic_lpi_tables_init();
+
+	return mem_info_parse_fixup(fdt);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig
new file mode 100644
index 0000000000..72015c6596
--- /dev/null
+++ b/configs/bcm_ns3_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_TARGET_BCMNS3=y
+CONFIG_SYS_TEXT_BASE=0xFF000000
+CONFIG_ENV_SIZE=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_LOGLEVEL=7
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+# CONFIG_SILENT_CONSOLE_UPDATE_ON_SET is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot> "
+CONFIG_SYS_XTRACE="n"
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_SWRITE=y
+# CONFIG_CMD_PINMUX is not set
+# CONFIG_CMD_SOURCE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="ns3-board"
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_IPROC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_FAT_WRITE=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/doc/README.bcmns3 b/doc/README.bcmns3
new file mode 100644
index 0000000000..c51f91471f
--- /dev/null
+++ b/doc/README.bcmns3
@@ -0,0 +1,74 @@
+BCMNS3 QSPI memory layout
+=========================
+
+BCMNS3 has total 8MB non-volatile SPI flash memory. It is used to store
+different images like fip.bin, nitro firmware, DDR shmo value and other backup
+images.
+
+Following is the QSPI flash memory layout.
+
+/*         QSPI layout
+ * |---------------------------|->0x000000
+ * |                           |
+ * |                           |
+ * |        fip.bin            |
+ * |         2MB               |
+ * |                           |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |                           |
+ * |                           |
+ * |---------------------------|->0x200000
+ * |                           |
+ * |                           |
+ * |                           |
+ * |       fip.bin (Mirror)    |
+ * |        2MB                |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |                           |
+ * |                           |
+ * |---------------------------|->0x400000
+ * |                           |
+ * |      Nitro NS3 Config     |
+ * |          1.5M             |
+ * |                           |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |---------------------------|->0x580000
+ * |      Nitro NS3 Config     |
+ * |          1.5M             |
+ * |        (Mirror)           |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |---------------------------|->0x700000
+ * |   Nitro NS3 bspd Config   |
+ * |        64KB               |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |---------------------------|->0x710000
+ * |   Nitro NS3 bspd Config   |
+ * |        64KB               |
+ * ~       (Mirror)            ~
+ * ~                           ~
+ * |                           |
+ * |---------------------------|->0x720000
+ * |        SHMOO              |
+ * |        64KB               |
+ * |                           |
+ * ~                           ~
+ * ~                           ~
+ * |---------------------------|->0x730000
+ * |        Meta Data          |
+ * |        832KB              |
+ * |                           |
+ * ~                           ~
+ * ~                           ~
+ * |                           |
+ * |---------------------------|
+ */
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c1928442be..ff5cd7efce 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -154,6 +154,17 @@ config IMX_RGPIO2P
 	help
 	  This driver supports i.MX7ULP Rapid GPIO2P controller.
 
+config IPROC_GPIO
+	bool "Broadcom iProc GPIO driver(without pinconf)"
+	default n
+	help
+	  The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray,
+	  use the same GPIO Controller IP hence this driver could be used
+	  for all.
+
+	  The Broadcom iProc based SoCs have multiple GPIO controllers and only
+	  the always-ON GPIO controller (CRMU/AON) is supported by this driver.
+
 config HSDK_CREG_GPIO
 	bool "HSDK CREG GPIO griver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 334c5f27fe..e769509c69 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CORTINA_GPIO)      += cortina_gpio.o
 obj-$(CONFIG_INTEL_GPIO)	+= intel_gpio.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
 obj-$(CONFIG_INTEL_BROADWELL_GPIO)	+= intel_broadwell_gpio.o
+obj-$(CONFIG_IPROC_GPIO)	+= iproc_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c
new file mode 100644
index 0000000000..cc26a1306b
--- /dev/null
+++ b/drivers/gpio/iproc_gpio.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier:      GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/pinctrl.h>
+
+/*
+ * There are five GPIO bank register. Each bank can configure max of 32 gpios.
+ * BANK0 - gpios 0 to 31
+ * BANK1 - gpios 32 to 63
+ * BANK2 - gpios 64 to 95
+ * BANK3 - gpios 96 to 127
+ * BANK4 - gpios 128 to 150
+ *
+ * Offset difference between consecutive bank register is 0x200
+ */
+#define NGPIO_PER_BANK		32
+#define GPIO_BANK_SIZE		0x200
+#define GPIO_BANK(pin)		((pin) / NGPIO_PER_BANK)
+#define GPIO_SHIFT(pin)		((pin) % NGPIO_PER_BANK)
+#define GPIO_REG(pin, reg)	(GPIO_BANK_SIZE * GPIO_BANK(pin) + (reg))
+
+/* device register offset */
+#define DATA_IN_OFFSET   0x00
+#define DATA_OUT_OFFSET  0x04
+#define OUT_EN_OFFSET    0x08
+
+/**
+ * struct iproc_gpio_pctrl_map - gpio and pinctrl mapping
+ * @gpio_pin:	start of gpio number in gpio-ranges
+ * @pctrl_pin:	start of pinctrl number in gpio-ranges
+ * @npins:	total number of pins in gpio-ranges
+ * @node:	list node
+ */
+struct iproc_gpio_pctrl_map {
+	u32 gpio_pin;
+	u32 pctrl_pin;
+	u32 npins;
+	struct list_head node;
+};
+
+/**
+ * struct iproc_gpio_pctrl_map - gpio device instance
+ * @pinctrl_dev:pointer to pinctrl device
+ * @gpiomap:	list node having mapping between gpio and pinctrl
+ * @base:	I/O register base address of gpio device
+ * @name:	gpio device name, ex GPIO0, GPIO1
+ * @ngpios:	total number of gpios
+ */
+struct iproc_gpio_platdata {
+	struct udevice *pinctrl_dev;
+	struct list_head gpiomap;
+	void __iomem *base;
+	char *name;
+	u32 ngpios;
+};
+
+/**
+ * iproc_gpio_set_bit - set or clear one bit in an iproc GPIO register.
+ *
+ * The bit relates to a GPIO pin.
+ *
+ * @plat: iproc GPIO device
+ * @reg: register offset
+ * @gpio: GPIO pin
+ * @set: set or clear
+ */
+static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
+				      u32 reg, u32 gpio, bool set)
+{
+	u32 offset = GPIO_REG(gpio, reg);
+	u32 shift = GPIO_SHIFT(gpio);
+
+	clrsetbits_le32(plat->base + offset, BIT(shift),
+			(set ? BIT(shift) : 0));
+}
+
+static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
+				      u32 reg, u32 gpio)
+{
+	u32 offset = GPIO_REG(gpio, reg);
+	u32 shift = GPIO_SHIFT(gpio);
+
+	return readl(plat->base + offset) & BIT(shift);
+}
+
+/**
+ * iproc_get_gpio_pctrl_mapping() - get associated pinctrl pin from gpio pin
+ *
+ * @plat: iproc GPIO device
+ * @gpio: GPIO pin
+ */
+static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32 gpio)
+{
+	struct iproc_gpio_pctrl_map *range = NULL;
+	struct list_head *pos, *tmp;
+	u32 ret = 0;
+
+	list_for_each_safe(pos, tmp, &plat->gpiomap) {
+		range = list_entry(pos, struct iproc_gpio_pctrl_map, node);
+		if (gpio == range->gpio_pin ||
+		    gpio < (range->gpio_pin + range->npins)) {
+			ret = range->pctrl_pin + (gpio - range->gpio_pin);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * iproc_get_gpio_pctrl_mapping() - get mapping between gpio and pinctrl
+ *
+ * Read dt node "gpio-ranges" to get gpio and pinctrl mapping and store
+ * in private data structure to use it later while enabling gpio.
+ *
+ * @dev: pointer to GPIO device
+ * @return 0 on success and -ENOMEM on failure
+ */
+static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+	struct iproc_gpio_pctrl_map *range = NULL;
+	struct ofnode_phandle_args args;
+	int index = 0, ret;
+
+	for (;; index++) {
+		ret = dev_read_phandle_with_args(dev, "gpio-ranges",
+						 NULL, 3, index, &args);
+		if (ret)
+			break;
+
+		range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
+		if (!range)
+			return -ENOMEM;
+
+		range->gpio_pin = args.args[0];
+		range->pctrl_pin = args.args[1];
+		range->npins = args.args[2];
+		list_add_tail(&range->node, &plat->gpiomap);
+	}
+
+	return 0;
+}
+
+static int iproc_gpio_request(struct udevice *dev, u32 gpio, const char *label)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 pctrl;
+
+	/* nothing to do if there is no corresponding pinctrl device */
+	if (!plat->pinctrl_dev)
+		return 0;
+
+	pctrl = iproc_get_pctrl_from_gpio(plat, gpio);
+
+	return pinctrl_request(plat->pinctrl_dev, pctrl, 0);
+}
+
+static int iproc_gpio_direction_input(struct udevice *dev, u32 gpio)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+
+	iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, false);
+	dev_dbg(dev, "gpio:%u set input\n", gpio);
+
+	return 0;
+}
+
+static int iproc_gpio_direction_output(struct udevice *dev, u32 gpio, int value)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+
+	iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, true);
+	iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
+	dev_dbg(dev, "gpio:%u set output, value:%d\n", gpio, value);
+
+	return 0;
+}
+
+static int iproc_gpio_get_value(struct udevice *dev, u32 gpio)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+	int value;
+
+	value = iproc_gpio_get_bit(plat, DATA_IN_OFFSET, gpio);
+	dev_dbg(dev, "gpio:%u get, value:%d\n", gpio, value);
+
+	return value;
+}
+
+static int iproc_gpio_set_value(struct udevice *dev, u32 gpio, int value)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+
+	if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
+		iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
+
+	dev_dbg(dev, "gpio:%u set, value:%d\n", gpio, value);
+	return 0;
+}
+
+static int iproc_gpio_get_function(struct udevice *dev, u32 gpio)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+
+	if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int iproc_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	int ret;
+	char name[10];
+
+	plat->base = dev_read_addr_ptr(dev);
+	if (!plat->base) {
+		debug("%s: Failed to get base address\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dev_read_u32(dev, "ngpios", &plat->ngpios);
+	if (ret < 0) {
+		dev_err(dev, "%s: Failed to get ngpios\n", __func__);
+		return ret;
+	}
+
+	uclass_get_device_by_phandle(UCLASS_PINCTRL, dev, "gpio-ranges",
+				     &plat->pinctrl_dev);
+	if (ret < 0) {
+		dev_err(dev, "%s: Failed to get pinctrl phandle\n", __func__);
+		return ret;
+	}
+
+	INIT_LIST_HEAD(&plat->gpiomap);
+	ret = iproc_get_gpio_pctrl_mapping(dev);
+	if (ret < 0) {
+		dev_err(dev, "%s: Failed to get gpio to pctrl map ret(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	snprintf(name, sizeof(name), "GPIO%d", dev->req_seq);
+	plat->name = strdup(name);
+	if (!plat->name)
+		return -ENOMEM;
+
+	uc_priv->gpio_count = plat->ngpios;
+	uc_priv->bank_name = plat->name;
+
+	dev_info(dev, ":bank name(%s) base %p, #gpios %d\n",
+		 plat->name, plat->base, plat->ngpios);
+
+	return 0;
+}
+
+static const struct dm_gpio_ops iproc_gpio_ops = {
+	.request		= iproc_gpio_request,
+	.direction_input	= iproc_gpio_direction_input,
+	.direction_output	= iproc_gpio_direction_output,
+	.get_value		= iproc_gpio_get_value,
+	.set_value		= iproc_gpio_set_value,
+	.get_function		= iproc_gpio_get_function,
+};
+
+static const struct udevice_id iproc_gpio_ids[] = {
+	{ .compatible = "brcm,iproc-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(iproc_gpio) = {
+	.name			= "iproc_gpio",
+	.id			= UCLASS_GPIO,
+	.of_match		= iproc_gpio_ids,
+	.ops			= &iproc_gpio_ops,
+	.ofdata_to_platdata	= iproc_gpio_ofdata_to_platdata,
+	.platdata_auto_alloc_size	= sizeof(struct iproc_gpio_platdata),
+};
diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig
index 5c0c89043f..5ca5a0836c 100644
--- a/drivers/tee/Kconfig
+++ b/drivers/tee/Kconfig
@@ -29,6 +29,7 @@ config SANDBOX_TEE
 	  "avb" commands.
 
 source "drivers/tee/optee/Kconfig"
+source "drivers/tee/broadcom/Kconfig"
 
 endmenu
 
diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile
index f72c68c09f..5c8ffdbce8 100644
--- a/drivers/tee/Makefile
+++ b/drivers/tee/Makefile
@@ -3,3 +3,4 @@
 obj-y += tee-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox.o
 obj-$(CONFIG_OPTEE) += optee/
+obj-y += broadcom/
diff --git a/drivers/tee/broadcom/Kconfig b/drivers/tee/broadcom/Kconfig
new file mode 100644
index 0000000000..ce95072d4e
--- /dev/null
+++ b/drivers/tee/broadcom/Kconfig
@@ -0,0 +1,7 @@
+config CHIMP_OPTEE
+	bool "Enable secure ChiMP firmware loading"
+	depends on OPTEE
+	default y
+	help
+	  This driver is used to load bnxt firmware binary using OpTEE.
+	  bnxt is Broadcom NetXtreme controller Ethernet card.
diff --git a/drivers/tee/broadcom/Makefile b/drivers/tee/broadcom/Makefile
new file mode 100644
index 0000000000..cb3cef16df
--- /dev/null
+++ b/drivers/tee/broadcom/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += chimp_optee.o
diff --git a/drivers/tee/broadcom/chimp_optee.c b/drivers/tee/broadcom/chimp_optee.c
new file mode 100644
index 0000000000..37f9b094f7
--- /dev/null
+++ b/drivers/tee/broadcom/chimp_optee.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2020 Broadcom.
+ */
+
+#include <common.h>
+#include <tee.h>
+#include <broadcom/chimp.h>
+
+#ifdef CONFIG_CHIMP_OPTEE
+
+#define CHMIP_BOOT_UUID { 0x6272636D, 0x2019, 0x0716, \
+		   { 0x42, 0x43, 0x4D, 0x5F, 0x53, 0x43, 0x48, 0x49 } }
+
+enum {
+	TEE_CHIMP_FASTBOOT = 0,
+	TEE_CHIMP_HEALTH_STATUS,
+	TEE_CHIMP_HANDSHAKE_STATUS,
+} tee_chmip_cmd;
+
+struct bcm_chimp_data {
+	struct udevice *tee;
+	u32 session;
+} chimp_data;
+
+static int get_open_session(struct bcm_chimp_data *b_data)
+{
+	const struct tee_optee_ta_uuid uuid = CHMIP_BOOT_UUID;
+	struct tee_open_session_arg arg;
+	struct udevice *tee = NULL;
+	int rc;
+
+	tee = tee_find_device(NULL, NULL, NULL, NULL);
+	if (!tee)
+		return -ENODEV;
+
+	memset(&arg, 0, sizeof(arg));
+	tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
+	rc = tee_open_session(tee, &arg, 0, NULL);
+	if (rc < 0)
+		return -ENODEV;
+
+	b_data->tee = tee;
+	b_data->session = arg.session;
+
+	return 0;
+}
+
+static int init_arg(struct tee_invoke_arg *arg, u32 func)
+{
+	if (get_open_session(&chimp_data))
+		return -EINVAL;
+
+	memset(arg, 0, sizeof(struct tee_invoke_arg));
+	arg->func = func;
+	arg->session = chimp_data.session;
+
+	return 0;
+}
+
+int chimp_handshake_status_optee(u32 timeout, u32 *hs)
+{
+	struct tee_invoke_arg arg;
+	struct tee_param param[1];
+	int ret;
+
+	ret = init_arg(&arg, TEE_CHIMP_HANDSHAKE_STATUS);
+	if (ret < 0)
+		return ret;
+
+	param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT;
+	param[0].u.value.a = timeout;
+
+	ret = tee_invoke_func(chimp_data.tee, &arg, ARRAY_SIZE(param), param);
+	if (ret < 0) {
+		printf("Handshake status command failed\n");
+		goto out;
+	}
+
+	switch (arg.ret) {
+	case TEE_SUCCESS:
+		*hs = param[0].u.value.a;
+		ret =  0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+out:
+	tee_close_session(chimp_data.tee, chimp_data.session);
+	chimp_data.tee = NULL;
+
+	return ret;
+}
+
+int chimp_health_status_optee(u32 *health)
+{
+	struct tee_invoke_arg arg;
+	struct tee_param param[1];
+	int ret;
+
+	ret = init_arg(&arg, TEE_CHIMP_HEALTH_STATUS);
+	if (ret < 0)
+		return ret;
+
+	param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT;
+
+	ret = tee_invoke_func(chimp_data.tee, &arg, ARRAY_SIZE(param), param);
+	if (ret < 0) {
+		printf("Helath status command failed\n");
+		goto out;
+	}
+
+	switch (arg.ret) {
+	case TEE_SUCCESS:
+		*health = param[0].u.value.a;
+		ret =  0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+out:
+	tee_close_session(chimp_data.tee, chimp_data.session);
+	chimp_data.tee = NULL;
+
+	return ret;
+}
+
+int chimp_fastboot_optee(void)
+{
+	struct tee_invoke_arg arg;
+	int ret;
+
+	ret = init_arg(&arg, TEE_CHIMP_FASTBOOT);
+	if (ret < 0)
+		return ret;
+
+	ret = tee_invoke_func(chimp_data.tee, &arg, 0, NULL);
+	if (ret < 0) {
+		printf("Chimp boot_fail\n");
+		goto out;
+	}
+
+	switch (arg.ret) {
+	case TEE_SUCCESS:
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+out:
+	tee_close_session(chimp_data.tee, chimp_data.session);
+	chimp_data.tee = NULL;
+
+	return ret;
+}
+#else
+int chimp_handshake_status_optee(u32 timeout, u32 *status)
+{
+	printf("ChiMP handshake status fail (OPTEE not enabled)\n");
+
+	return -EINVAL;
+}
+
+int chimp_health_status_optee(u32 *status)
+{
+	printf("ChiMP health status fail (OPTEE not enabled)\n");
+
+	return -EINVAL;
+}
+
+int chimp_fastboot_optee(void)
+{
+	printf("ChiMP secure boot fail (OPTEE not enabled)\n");
+
+	return -EINVAL;
+}
+#endif /* CONFIG_CHIMP_OPTEE */
diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h
new file mode 100644
index 0000000000..7f64152913
--- /dev/null
+++ b/include/broadcom/chimp.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#ifndef __CHIMP_H__
+#define __CHIMP_H__
+
+#include <linux/compiler.h>
+
+/**
+ * chimp_fastboot_optee() - api to load bnxt firmware
+ *
+ * @return: 0 on success and -ve on failure
+ */
+int chimp_fastboot_optee(void);
+
+/**
+ * chimp_health_status_optee() - get chimp health status
+ *
+ * Chimp health status could be firmware is in good condition or
+ * bad condition because of crash/hang.
+ *
+ * @status: pointer to get chimp health status
+ *
+ * @return: 0 on success and -ve on failure
+ */
+int chimp_health_status_optee(u32 *status);
+
+/**
+ * chimp_handshake_status_optee() - get chimp handshake status.
+ *
+ * To know firmware is loaded and running.
+ *
+ * @timeout: timeout value, if 0 then default timeout is considered by op-tee
+ * @hstatus: pointer to chimp handshake status
+ *
+ * @return: 0 on success and -ve on failure
+ */
+int chimp_handshake_status_optee(u32 timeout, u32 *hstatus);
+
+#endif
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
new file mode 100644
index 0000000000..039f4d6759
--- /dev/null
+++ b/include/configs/bcm_ns3.h
@@ -0,0 +1,823 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#ifndef __BCM_NS3_H
+#define __BCM_NS3_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME			"NS3"
+
+/* Physical Memory Map */
+#define V2M_BASE			0x80000000
+#define PHYS_SDRAM_1			V2M_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x80000)
+
+/*
+ * Initial SP before reloaction is placed at end of first DRAM bank,
+ * which is 0x1_0000_0000.
+ * Just before re-loaction, new SP is updated and re-location happens.
+ * So pointing the initial SP to end of 2GB DDR is not a problem
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(PHYS_SDRAM_1 + 0x80000000)
+/* 12MB Malloc size */
+#define CONFIG_SYS_MALLOC_LEN		(SZ_8M + SZ_4M)
+
+/* console configuration */
+#define CONFIG_SYS_NS16550_CLK		25000000
+
+#define CONFIG_SYS_CBSIZE		SZ_1K
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * Increase max uncompressed/gunzip size, keeping size same as EMMC linux
+ * partition.
+ */
+#define CONFIG_SYS_BOOTM_LEN		0x01800000
+
+/* Env configuration */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+
+/* Access eMMC Boot_1 and Boot_2 partitions */
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* enable 64-bit PCI resources */
+#define CONFIG_SYS_PCI_64BIT		1
+
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=8\0"
+#define OS_LOG_LEVEL "log_level=loglevel=7\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x68A10000 " \
+		   "earlyelog=" __stringify(ELOG_AP_UART_LOG_BASE) ",0x10000 " \
+		   "crashkernel=512M reboot=w\0"
+
+#define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\0"
+
+#ifdef CONFIG_BCM_SF2_ETH
+#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0"
+#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \
+	"ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off"
+#else
+#define ETH_ADDR
+#define NET_ARGS
+#endif
+
+#define RESERVED_MEM "reserved_mem=memmap=0xff000000$0x1000000\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
+		  " ${max_cpus}  ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS " " NET_ARGS "\0"
+
+#define UPDATEME_FLASH_PARAMS "bcm_compat_level=4\0" \
+			      "bcm_need_recovery_rootfs=0\0" \
+			      "bcm_bl_flash_pending_rfs_imgs=0\0"
+
+#define KERNEL_LOADADDR_CFG \
+	"fit_image_loadaddr=0x90000000\0" \
+	"dtb_loadaddr=0x82000000\0"
+
+#define INITRD_ARGS "initrd_args=root=/dev/ram rw\0"
+#define INITRD_LOADADDR "initrd_loadaddr=0x92000000\0"
+#define INITRD_IMAGE "initrd_image=rootfs-lake-bcm958742t.cpio.gz\0"
+#define MMC_DEV "sd_device_number=0\0"
+#define EXEC_STATE "exec_state=normal\0"
+
+#define EXT4RD_ARGS "ext4rd_args="\
+	"root=/dev/mmcblk${sd_device_number}p${gpt_partition_entry} rw rootwait\0"
+
+#define WDT_CNTRL "wdt_enable=1\0" \
+		  "wdt_timeout_sec=0\0"
+
+#define ELOG_SETUP \
+	"mbox0_addr=0x66424024\0"\
+	"elog_setup="\
+	"if logsetup -s ${mbox0_addr}; then "\
+	"else "\
+		"echo ELOG is not supported by this version of the MCU patch.;"\
+		"exit;"\
+	"fi;"\
+	"if logsetup -c ${mbox0_addr}; then "\
+		"echo ELOG is ready;"\
+	"else "\
+		"echo ELOG is supported, but is not set up.;"\
+		"echo Getting setup file from the server ${serverip}...;"\
+		"if tftp ${tftp_dir}elog_src.txt; then "\
+			"echo Setting up ELOG. Please wait...;"\
+			"if logsetup ${loadaddr} ${mbox0_addr} ${filesize}; "\
+				"then "\
+			"else "\
+				"echo [logsetup] ERROR.;"\
+			"fi;"\
+			"if logsetup -c ${mbox0_addr}; then "\
+				"echo ELOG is READY.;"\
+			"else "\
+				"echo ELOG is NOT SET UP.;"\
+			"fi;"\
+		"else "\
+			"echo ELOG setup file is not available on the server.;"\
+		"fi;"\
+	"fi \0"
+
+/* eMMC partition for FIT images */
+#define FIT_MMC_PARTITION \
+	"fit_partitions=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=env,size=512K,uuid=${uuid_gpt_env};" \
+	"name=Image_rsa.img,size=24MiB,uuid=${uuid_gpt_linux};" \
+	"name=Image1_rsa.img,size=24MiB,uuid=${uuid_gpt_linux1};" \
+	"name=Image2_rsa.img,size=24MiB,uuid=${uuid_gpt_linux2};" \
+	"name=nitro,size=8MiB,uuid=${uuid_gpt_nitro};" \
+	"name=recovery,size=940MiB,uuid=${uuid_gpt_recovery};" \
+	"name=rootfs,size=-,uuid=${uuid_gpt_prootfs}\0"
+
+#define QSPI_FLASH_NITRO_PARAMS \
+	"spi_nitro_img_bin_start=0x400000\0" \
+	"spi_nitro_img_bin_mirror_start=0x580000\0" \
+	"spi_nitro_bspd_cfg_start=0x700000\0" \
+	"spi_nitro_bspd_mirror_cfg_start=0x710000\0" \
+
+#define QSPI_ACCESS_ENABLE \
+	"qspi_access_en=" \
+	"mw 0x68a403e8 1;" \
+	"mw 0x68a403ec 1;" \
+	"mw 0x68a403f0 1;" \
+	"mw 0x68a403f4 1;" \
+	"mw 0x68a403f8 1;" \
+	"mw 0x68a403fc 1 \0"
+
+#define FUNC_QSPI_PROBE \
+	"func_qspi_probe="\
+	"if run qspi_access_en; then "\
+	"else "\
+		"echo ${errstr} run qspi_access_en ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf probe 0; then "\
+	"else "\
+		"echo echo ${errstr} sf probe command ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define NITRO_FW_IMAGES \
+	"nitro_bin=nitro.img\0" \
+	"nitro_bspd_cfg=nitro_fb_bspd_config.bin\0"
+
+#define FASTBOOT_NITRO_SETUP \
+	"nitro_fastboot_type=1\0" \
+	"nitro_fastboot_secure=1\0" \
+	"nitro_fastboot_img_buffer=0\0" \
+	"nitro_fit_img_loc=0x90000000\0"
+
+#define FASTBOOT_SETUP \
+	"fastboot_nitro_setup=" \
+	"setenv errstr fastboot_setup;" \
+	"run func_qspi_probe;" \
+	/* first load header only */ \
+	"if sf read ${nitro_fit_img_loc} "\
+		   "${spi_nitro_img_bin_start} 0x18; then "\
+	"else "\
+		"echo [fastboot_nitro_setup] sf read "\
+		      "${spi_nitro_img_bin_start} ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if spi_nitro_images_addr ${nitro_fit_img_loc} "\
+				 "${spi_nitro_img_bin_start}; then "\
+	"else "\
+		 "echo [fastboot_nitro_setup] spi_nitro_images_addr "\
+		       "** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define CHECK_CHIMP_HS\
+	"check_chimp_hs=chimp_hs"\
+	"\0"
+
+#define FASTBOOT_NITRO "fastboot_nitro=chimp_ld_secure\0"
+
+#define FIT_IMAGE "fit_image=Image_rsa.img\0"
+#define BOOTCMD_MMC_FIT \
+	"bootcmd_mmc_fit="\
+	"mmc dev ${sd_device_number};"\
+	"if test $exec_state = normal; then " \
+		"setenv use_rootfs rootfs;"\
+	"else " \
+		"setenv use_rootfs recovery;"\
+	"fi;" \
+	"echo used filesystem :${use_rootfs};"\
+	"gpt setenv mmc ${sd_device_number} ${use_rootfs};"\
+	"setenv bootargs_fs ${setbootargs} ${ext4rd_args}; run bootargs_fs;"\
+	"gpt setenv mmc ${sd_device_number} ${fit_image};"\
+	"mmc read ${fit_image_loadaddr} ${gpt_partition_addr} "\
+	"${gpt_partition_size};"\
+	"bootm ${fit_image_loadaddr}\0"
+
+#define BOOTCMD_MMC_FITS \
+	"bootcmd_mmc_fits="\
+	"setenv mmc_fit0 " \
+	"'setenv fit_image Image_rsa.img; run bootcmd_mmc_fit';"\
+	"setenv mmc_fit1 " \
+	"'setenv fit_image Image1_rsa.img; run bootcmd_mmc_fit';"\
+	"setenv mmc_fit2 " \
+	"'setenv fit_image Image2_rsa.img; run bootcmd_mmc_fit';"\
+	"run mmc_fit0 || run mmc_fit1 || run mmc_fit2\0"
+
+#define USBDEV "usbdev=0\0"
+#define BOOTCMD_USB\
+	"bootcmd_usb="\
+	"setenv usb_image_loadaddr 90000000;"\
+	"setenv fit_image Image_rsa.img;"\
+	"setenv bootargs_fs ${setbootargs} ${initrd_args}; run bootargs_fs;"\
+	"if usb dev ${usbdev}; && usb start; then "\
+		"echo Booting from USB...;"\
+		"fatload usb ${usbdev} ${usb_image_loadaddr} ${fit_image};"\
+		"fatload usb ${usbdev} ${initrd_loadaddr} ${initrd_image};"\
+		"bootm ${usb_image_loadaddr} ${initrd_loadaddr}:${filesize};"\
+	"fi;"\
+	"\0"
+
+#define START_PCI\
+	"start_pci=pci e "\
+	"\0"
+
+#define BNXT_LOAD\
+	"bnxt_load=bnxt 0 probe "\
+	"\0"
+
+#define BOOTCMD_PXE\
+	"bootcmd_pxe="\
+	"run check_chimp_hs && "\
+	"run start_pci && "\
+	"run bnxt_load;"\
+	"setenv ethact bnxt_eth0;"\
+	"setenv autoload no;"\
+	"setenv bootargs_fs ${setbootargs} ${initrd_args}; run bootargs_fs;"\
+	"if dhcp; then "\
+		"setenv pxefile_addr_r ${loadaddr};"\
+		"if pxe get; then "\
+			"setenv ramdisk_addr_r ${initrd_loadaddr};"\
+			"setenv kernel_addr_r ${fit_image_loadaddr};"\
+			"pxe boot; "\
+		"fi;"\
+	"fi;"\
+	"\0"
+
+#define FLASH_PENDING_RFS_IMGS \
+	"flash_pending_rfs_imgs=" \
+	"if test $bcm_bl_flash_pending_rfs_imgs = 1; then " \
+		"if test $bl_flash_pending_rfs_imgs = rootfs; then " \
+			"dhcp;" \
+			"run mmc_flash_rootfs;" \
+		"fi;" \
+		"if test $bl_flash_pending_rfs_imgs = recovery; then " \
+			"dhcp;" \
+			"run mmc_flash_recovery;" \
+		"fi;" \
+		"setenv bl_flash_pending_rfs_imgs;" \
+	"fi; \0"
+
+#define CONFIG_BOOTCOMMAND "run flash_pending_rfs_imgs;" \
+			   "run fastboot_nitro && "\
+			   "run bootcmd_mmc_fits || "\
+			   "run bootcmd_usb || "\
+			   "run bootcmd_pxe"
+
+/* Flashing commands */
+#define TFTP_QSPI_PARAM \
+	"fip_qspi_addr=0x0\0"\
+	"fip_qspi_mirror_addr=0x200000\0"\
+	"loadaddr=0x90000000\0"\
+	"tftpblocksize=1468\0"\
+	"qspi_flash_fip=fip\0"\
+
+/* Flash fit_GPT partition to eMMC */
+#define MMC_FLASH_FIT_GPT \
+	"mmc_flash_gpt="\
+	"if mmc dev ${sd_device_number}; then "\
+	"else "\
+		"echo [mmc_flash_gpt] mmc dev ${sd_device_number} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if gpt write mmc ${sd_device_number} ${fit_partitions}; then "\
+	"else "\
+		"echo [mmc_flash_gpt] gpt write ${fit_partitions} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define MMC_FLASH_IMAGE_RSA \
+	"mmc_flash_image_rsa="\
+	"if mmc dev ${sd_device_number}; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] mmc dev ${sd_device_number} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if gpt setenv mmc ${sd_device_number} ${fit_image}; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] gpt setenv ${fit_image} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if tftp ${loadaddr} ${tftp_dir}${fit_image}; then "\
+		"if test ${fit_image} = Image_rsa.img; then "\
+			"if setenv tftp_fit_image yes; then "\
+			"else "\
+				"echo [mmc_flash_image_rsa] "\
+				"setenv tftp_fit_image to yes"\
+				"** FAILED **;"\
+				"exit;"\
+			"fi;"\
+		"fi;"\
+	"else "\
+		"if test ${fit_image} = Image_rsa.img; then "\
+			"echo [mmc_flash_image_rsa] tftp "\
+			"${tftp_dir}${fit_image} ** FAILED **;"\
+		"else "\
+			"if test ${tftp_fit_image} = yes; then "\
+				"if mmc write ${loadaddr} "\
+				"${gpt_partition_addr} "\
+				"${fileblocks}; then "\
+				"else "\
+					"echo "\
+					"[mmc_flash_image_rsa] "\
+					"mmc write "\
+					"${gpt_partition_addr} "\
+					"** FAILED **;"\
+					"exit;"\
+				"fi;"\
+			"else "\
+				"echo [mmc_flash_image_rsa] tftp "\
+				"${tftp_dir}${fit_image} "\
+				"** FAILED **;"\
+			"fi;"\
+		"fi;"\
+		"exit;"\
+	"fi;"\
+	"if math add filesize filesize 1FF; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] math add command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math div fileblocks filesize 200; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] math div command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if mmc write ${loadaddr} ${gpt_partition_addr} ${fileblocks}; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] mmc write ${gpt_partition_addr} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if setenv image_sz_blk_cnt ${fileblocks}; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] setenv image_sz_blk_cnt ** "\
+		"FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if saveenv; then "\
+	"else "\
+		"echo [mmc_flash_image_rsa] saveenv command ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define MMC_FLASH_RECOVERY \
+	"mmc_flash_recovery="\
+	"if mmc dev ${sd_device_number}; then "\
+	"else "\
+		"echo [mmc_flash_recovery] mmc dev ${sd_device_number} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if gpt setenv mmc ${sd_device_number} recovery; then "\
+	"else "\
+		"echo [mmc_flash_recovery] gpt setenv recovery ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"setenv index 1;"\
+	"while tftp ${loadaddr} "\
+	"${tftp_dir}${gpt_partition_name}/chunk_00${index}; do "\
+		"if math add filesize filesize 1FF; then "\
+		"else "\
+			"echo [mmc_flash_recovery] math add command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math div fileblocks filesize 200; then "\
+		"else "\
+			"echo [mmc_flash_recovery] math div command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if mmc write ${loadaddr} ${gpt_partition_addr} "\
+		"${fileblocks}; then "\
+		"else "\
+			"echo [mmc_flash_recovery] mmc write "\
+			"${gpt_partition_addr} ** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math add index index 1; then "\
+		"else "\
+			"echo [mmc_flash_recovery] math add command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math add gpt_partition_addr gpt_partition_addr"\
+		" ${fileblocks}; then "\
+		"else "\
+			"echo [mmc_flash_recovery] math add command"\
+			" ** FAILED **;"\
+			"exit;"\
+		"fi;"\
+	"done;"\
+	"if itest ${index} -ne 1; then "\
+	"else "\
+		"echo [mmc_flash_recovery] "\
+		"${tftp_dir}${gpt_partition_name}/chunk_00${index} file "\
+		"not found ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define MMC_FLASH_ROOTFS \
+	"mmc_flash_rootfs="\
+	"if mmc dev ${sd_device_number}; then "\
+	"else "\
+		"echo [mmc_flash_rootfs] mmc dev ${sd_device_number} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if gpt setenv mmc ${sd_device_number} rootfs; then "\
+	"else "\
+		"echo [mmc_flash_rootfs] gpt setenv rootfs ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"setenv index 1;"\
+	"while tftp ${loadaddr} "\
+	"${tftp_dir}${gpt_partition_name}/chunk_00${index}; do "\
+		"if math add filesize filesize 1FF; then "\
+		"else "\
+			"echo [mmc_flash_rootfs] math add command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math div fileblocks filesize 200; then "\
+		"else "\
+			"echo [mmc_flash_rootfs] math div command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if mmc write ${loadaddr} ${gpt_partition_addr} "\
+		"${fileblocks}; then "\
+		"else "\
+			"echo [mmc_flash_rootfs] mmc write "\
+			"${gpt_partition_addr} ** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math add index index 1; then "\
+		"else "\
+			"echo [mmc_flash_rootfs] math add command "\
+			"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if math add gpt_partition_addr gpt_partition_addr"\
+		" ${fileblocks}; then "\
+		"else "\
+			"echo [mmc_flash_rootfs] math add command"\
+			" ** FAILED **;"\
+			"exit;"\
+		"fi;"\
+	"done;"\
+	"if itest ${index} -ne 1; then "\
+	"else "\
+		"echo [mmc_flash_rootfs] "\
+		"${tftp_dir}${gpt_partition_name}/chunk_00${index} file "\
+		"not found ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+/*
+ * For individual flash commands like mmc_flash_gpt, it is not
+ * necessary to check for errors.
+ * If any of its intermediate commands fails, then next commands
+ * will not execute. Script will exit from the failure command.
+ * For uniformity, checking for mmc_flash_gpt, mmc_flash_image_rsa
+ * mmc_flash_nitro and mmc_flash_rootfs
+ */
+#define MMC_FLASH \
+	"flash_mmc="\
+	"if run mmc_flash_gpt; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_gpt ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if setenv tftp_fit_image no; then "\
+	"else "\
+		"echo [flash_mmc] setenv tftp_fit_image to no "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if setenv fit_image Image_rsa.img; then "\
+	"else "\
+		"echo [flash_mmc] setenv fit_image to Image_rsa.img "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run mmc_flash_image_rsa; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_image_rsa ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if setenv fit_image Image1_rsa.img; then "\
+	"else "\
+		"echo [flash_mmc] setenv fit_image to Image1_rsa.img "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run mmc_flash_image_rsa; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_image_rsa "\
+		"for Image1_rsa.img ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if setenv fit_image Image2_rsa.img; then "\
+	"else "\
+		"echo [flash_mmc] setenv fit_image to Image2_rsa.img "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run mmc_flash_image_rsa; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_image_rsa "\
+		"for Image2_rsa.img ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run mmc_flash_recovery; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_recovery ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run mmc_flash_rootfs; then "\
+	"else "\
+		"echo [flash_mmc] run mmc_flash_rootfs ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define FUNC_ALIGN_QSPI_ERASE_BLOCK_SIZE \
+	"align_erase_blk_size=" \
+	"setenv fl_write_size 0;" \
+	"if math add fl_write_size filesize FFFF; then "\
+	"else "\
+		"echo ${errstr} math add command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math div fl_write_size fl_write_size 10000; then "\
+	"else "\
+		"echo ${errstr} math div command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math mul fl_write_size fl_write_size 10000; then "\
+	"else "\
+		"echo ${errstr} math mul command ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define QSPI_FLASH_FIP \
+	"flash_fip="\
+	"if run qspi_access_en; then "\
+	"else "\
+		"echo [flash_fip] run qspi_access_en ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if tftp ${loadaddr} ${tftp_dir}fip.bin; then "\
+	"else "\
+		"echo [flash_fip] tftp ${tftp_dir}fip.bin "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math add tmpsize filesize FFFF; then "\
+	"else "\
+		"echo [flash_fip] math add command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math div tmpsize tmpsize 10000; then "\
+	"else "\
+		"echo [flash_fip] math div command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if math mul tmpsize tmpsize 10000; then "\
+	"else "\
+		"echo [flash_fip] math mul command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf probe 0; then "\
+	"else "\
+		"echo [flash_fip] sf probe command ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf erase ${fip_qspi_addr} ${tmpsize}; then "\
+	"else "\
+		"echo [flash_fip] sf erase ${fip_qspi_addr} ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf write ${loadaddr} ${fip_qspi_addr} ${filesize}; then "\
+	"else "\
+		"echo [flash_fip] sf write ${fip_qspi_addr} ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	/* Flash mirror FIP image */ \
+	"if sf erase ${fip_qspi_mirror_addr} ${tmpsize}; then "\
+	"else "\
+		"echo [flash_fip] sf erase ${fip_qspi_mirror_addr} "\
+			"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf write ${loadaddr} ${fip_qspi_mirror_addr} ${filesize}; then "\
+	"else "\
+		"echo [flash_fip] sf write ${fip_qspi_mirror_addr} "\
+			"** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define QSPI_FLASH_NITRO \
+	"flash_nitro="\
+	"run func_qspi_probe; "\
+	"if tftp ${loadaddr} ${tftp_dir}${nitro_bin}; then "\
+	"else "\
+		"echo [flash_nitro] tftp ${tftp_dir}${nitro_bin} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"setenv errstr flash_nitro;" \
+	"run align_erase_blk_size;" \
+	/* Flash Nitro fw fit + configuration */ \
+	"if sf erase ${spi_nitro_img_bin_start} ${fl_write_size}; then "\
+	"else "\
+		"echo [flash_nitro] sf erase ${spi_nitro_img_bin_start} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf write ${loadaddr} ${spi_nitro_img_bin_start}" \
+		     " ${fl_write_size}; then "\
+	"else "\
+		"echo [flash_nitro] sf write ${spi_nitro_bin_start} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	/* Mirror of Flash Nitro fw fit + configuration */ \
+	"if sf erase ${spi_nitro_img_bin_mirror_start} ${fl_write_size}; then "\
+	"else "\
+		"echo [flash_nitro] sf erase "\
+		      "${spi_nitro_img_bin_mirror_start} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if sf write ${loadaddr} ${spi_nitro_img_bin_mirror_start}" \
+		     " ${fl_write_size}; then "\
+	"else "\
+		"echo [flash_nitro] sf write "\
+		      "${spi_nitro_img_bin_mirror_start} "\
+		"** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define QSPI_FLASH_NITRO_BSPD_CONFIG \
+	"flash_nitro_bspd_config="\
+	"run func_qspi_probe; "\
+	/* Flash BSPD configuration */ \
+	"if tftp ${loadaddr} ${tftp_dir}${nitro_bspd_cfg}; then "\
+		"setenv bspd_cfg_avialable 1; "\
+		"setenv errstr flash_nitro_bspd_config; "\
+		"run align_erase_blk_size;" \
+		"if sf erase ${spi_nitro_bspd_cfg_start} "\
+			    "${fl_write_size}; then "\
+		"else "\
+			"echo [flash_nitro] sf erase "\
+				"${spi_nitro_bspd_cfg_start} "\
+				"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if sf write ${loadaddr} ${spi_nitro_bspd_cfg_start} "\
+			    "${fl_write_size}; then "\
+		"else "\
+			"echo [flash_nitro] sf write "\
+				"${spi_nitro_bspd_cfg_start} "\
+				"** FAILED **;"\
+			"exit;"\
+		"fi;" \
+		/* Flash BSPD mirror configuration */ \
+		"if sf erase ${spi_nitro_bspd_mirror_cfg_start} "\
+			    "${fl_write_size}; then "\
+		"else "\
+			"echo [flash_nitro] sf erase "\
+				"${spi_nitro_bspd_mirror_cfg_start} "\
+				"** FAILED **;"\
+			"exit;"\
+		"fi;"\
+		"if sf write ${loadaddr} ${spi_nitro_bspd_mirror_cfg_start} "\
+			"${fl_write_size}; then "\
+		"else "\
+			"echo [flash_nitro] sf write "\
+				"${spi_nitro_bspd_mirror_cfg_start} "\
+				"** FAILED **;"\
+			"exit;"\
+		"fi;" \
+	"else "\
+		"echo [flash_nitro] tftp ${tftp_dir}${nitro_bspd_cfg} "\
+		"** Skip flashing bspd config file **;"\
+	"fi \0"
+
+#define QSPI_FLASH \
+	"flash_qspi="\
+	"if run qspi_access_en; then "\
+	"else "\
+		"echo [flash_qspi] run qspi_access_en ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run flash_fip; then "\
+	"else "\
+		"echo [flash_qspi] run flash_fip ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run flash_nitro; then "\
+	"else "\
+		"echo [flash_qspi] run flash_nitro ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define FLASH_IMAGES \
+	"flash_images=" \
+	"if run flash_qspi; then "\
+	"else "\
+		"echo [flash_images] run flash_qspi ** FAILED **;"\
+		"exit;"\
+	"fi;"\
+	"if run flash_mmc; then "\
+	"else "\
+		"echo [flash_images] run flash_mmc ** FAILED **;"\
+		"exit;"\
+	"fi \0"
+
+#define ARCH_ENV_SETTINGS \
+	CONSOLE_ARGS \
+	MAX_CPUS \
+	OS_LOG_LEVEL \
+	EXTRA_ARGS \
+	PCIE_ARGS \
+	ETH_ADDR \
+	RESERVED_MEM \
+	SETBOOTARGS \
+	UPDATEME_FLASH_PARAMS \
+	KERNEL_LOADADDR_CFG\
+	INITRD_ARGS \
+	INITRD_LOADADDR \
+	INITRD_IMAGE \
+	MMC_DEV \
+	EXEC_STATE \
+	EXT4RD_ARGS \
+	WDT_CNTRL \
+	ELOG_SETUP \
+	FIT_MMC_PARTITION \
+	QSPI_FLASH_NITRO_PARAMS \
+	QSPI_ACCESS_ENABLE \
+	FUNC_QSPI_PROBE \
+	NITRO_FW_IMAGES \
+	FASTBOOT_NITRO_SETUP \
+	FASTBOOT_SETUP \
+	CHECK_CHIMP_HS \
+	FASTBOOT_NITRO \
+	FIT_IMAGE \
+	BOOTCMD_MMC_FIT \
+	BOOTCMD_MMC_FITS \
+	USBDEV \
+	BOOTCMD_USB \
+	START_PCI \
+	BNXT_LOAD \
+	BOOTCMD_PXE \
+	FLASH_PENDING_RFS_IMGS \
+	TFTP_QSPI_PARAM \
+	MMC_FLASH_FIT_GPT \
+	MMC_FLASH_IMAGE_RSA \
+	MMC_FLASH_RECOVERY \
+	MMC_FLASH_ROOTFS \
+	MMC_FLASH \
+	FUNC_ALIGN_QSPI_ERASE_BLOCK_SIZE \
+	QSPI_FLASH_FIP \
+	QSPI_FLASH_NITRO \
+	QSPI_FLASH_NITRO_BSPD_CONFIG \
+	QSPI_FLASH \
+	FLASH_IMAGES
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ARCH_ENV_SETTINGS
+
+#endif /* __BCM_NS3_H */
diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h
new file mode 100644
index 0000000000..84795ec27a
--- /dev/null
+++ b/include/dt-bindings/memory/bcm-ns3-mc.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#ifndef DT_BINDINGS_BCM_NS3_MC_H
+#define DT_BINDINGS_BCM_NS3_MC_H
+
+/*
+ * +--------+----------+ 0x8b000000
+ * | NITRO CRASH DUMP  |  32MB
+ * +--------+----------+ 0x8d000000
+ * | SHMEM (NS)         | 16 MB
+ * +-------------------+ 0x8e000000
+ * |        | TEE_RAM(S)| 4MB
+ * + TZDRAM +----------+ 0x8e400000
+ * |        | TA_RAM(S) | 12MB
+ * +--------+----------+ 0x8f000000
+ * | BL31 + TMON + LPM  |
+ * | memory             | 1MB
+ * +-------------------+ 0x8f100000
+ */
+
+#define BCM_NS3_MEM_NITRO_CRASH_START  0x8ae00000
+#define BCM_NS3_MEM_NITRO_CRASH_LEN    0x21fffff
+#define BCM_NS3_MEM_NITRO_CRASH_SIZE   0x2200000
+
+#define BCM_NS3_MEM_SHARE_START    0x8d000000
+#define BCM_NS3_MEM_SHARE_LEN      0x020fffff
+
+/* ATF/U-boot/Linux error logs */
+#define BCM_NS3_MEM_ELOG_START     0x8f113000
+#define BCM_NS3_MEM_ELOG_LEN       0x00100000
+
+/* CRMU Page table memroy */
+#define BCM_NS3_MEM_CRMU_PT_START  0x880000000
+#define BCM_NS3_MEM_CRMU_PT_LEN    0x200000
+
+/* default memory starting address and length */
+#define BCM_NS3_MEM_START          0x80000000UL
+#define BCM_NS3_MEM_LEN            0x80000000UL
+#define BCM_NS3_MEM_END            (BCM_NS3_MEM_START + BCM_NS3_MEM_LEN)
+
+/* memory starting address and length for BANK_1 */
+#define BCM_NS3_BANK_1_MEM_START   0x880000000UL
+#define BCM_NS3_BANK_1_MEM_LEN     0x180000000UL
+
+/* memory layout information */
+#define BCM_NS3_DDR_INFO_BASE      0x8f220000
+#define BCM_NS3_DDR_INFO_RSVD_LEN  0x1000
+#define BCM_NS3_DDR_INFO_LEN       73
+#define BCM_NS3_DDR_INFO_SIG       0x42434d44
+#define BCM_NS3_MAX_NR_BANKS       4
+
+#define BCM_NS3_GIC_LPI_BASE      0x8ad70000
+#define BCM_NS3_MEM_RSVE_START    BCM_NS3_GIC_LPI_BASE
+#define BCM_NS3_MEM_RSVE_END      ((BCM_NS3_MEM_ELOG_START + \
+				   BCM_NS3_MEM_ELOG_LEN) - \
+				   BCM_NS3_MEM_RSVE_START)
+
+#define BCM_NS3_CRMU_PGT_START    0x880000000UL
+#define BCM_NS3_CRMU_PGT_SIZE     0x100000
+#endif
diff --git a/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h
new file mode 100644
index 0000000000..81ebd58ca5
--- /dev/null
+++ b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+
+/* Alternate functions available in MUX controller */
+#define MODE_NITRO				0
+#define MODE_NAND				1
+#define MODE_PNOR				2
+#define MODE_GPIO				3
+
+/* Pad configuration attribute */
+#define PAD_SLEW_RATE_ENA			BIT(0)
+#define PAD_SLEW_RATE_ENA_MASK			BIT(0)
+
+#define PAD_DRIVE_STRENGTH_2_MA			(0 << 1)
+#define PAD_DRIVE_STRENGTH_4_MA			BIT(1)
+#define PAD_DRIVE_STRENGTH_6_MA			(2 << 1)
+#define PAD_DRIVE_STRENGTH_8_MA			(3 << 1)
+#define PAD_DRIVE_STRENGTH_10_MA		(4 << 1)
+#define PAD_DRIVE_STRENGTH_12_MA		(5 << 1)
+#define PAD_DRIVE_STRENGTH_14_MA		(6 << 1)
+#define PAD_DRIVE_STRENGTH_16_MA		(7 << 1)
+#define PAD_DRIVE_STRENGTH_MASK			(7 << 1)
+
+#define PAD_PULL_UP_ENA				BIT(4)
+#define PAD_PULL_UP_ENA_MASK			BIT(4)
+
+#define PAD_PULL_DOWN_ENA			BIT(5)
+#define PAD_PULL_DOWN_ENA_MASK			BIT(5)
+
+#define PAD_INPUT_PATH_DIS			BIT(6)
+#define PAD_INPUT_PATH_DIS_MASK			BIT(6)
+
+#define PAD_HYSTERESIS_ENA			BIT(7)
+#define PAD_HYSTERESIS_ENA_MASK			BIT(7)
+
+#endif