diff options
| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2017-05-03 15:10:23 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2017-05-10 16:16:09 +0200 |
| commit | 78118211fb61df2f6427dc0ea7a65c97c20b3d11 (patch) | |
| tree | cdcffbd64906128f61a435788f1ec8f2fcf67182 | |
| parent | efe8b9d0122e5ab25f7284a36a716cd6610e8ad4 (diff) | |
| download | u-boot-78118211fb61df2f6427dc0ea7a65c97c20b3d11.tar.gz | |
mips: bmips: add bcm6345-rst driver support for BCM6328
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/mips/dts/brcm,bcm6328.dtsi | 7 | ||||
| -rw-r--r-- | include/dt-bindings/reset/bcm6328-reset.h | 24 |
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 6b5c5dd734..9b76a2322c 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/bcm6328-clock.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6328-reset.h> #include "skeleton.dtsi" / { @@ -58,6 +59,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + pll_cntl: syscon@10000068 { compatible = "syscon"; reg = <0x10000068 0x4>; diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 0000000000..c144ad2a78 --- /dev/null +++ b/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ |