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| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-10-20 11:03:02 +0530 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-10-26 10:01:37 +0800 |
| commit | 7257455e7cd8038263a738401cbfe0ee8a2c7ac9 (patch) | |
| tree | eb7ec9f8560ce0d39d1ceb4741514e571d91c135 | |
| parent | 47d7e3b5eb72fd540930c830d568ece19b3defa0 (diff) | |
| download | u-boot-7257455e7cd8038263a738401cbfe0ee8a2c7ac9.tar.gz | |
riscv: fu540: dts: Correct reg size of clint node
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
| -rw-r--r-- | arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index a06e1b11c6..b7cd600b8c 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -62,7 +62,7 @@ &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; - reg = <0x0 0x2000000 0x0 0xc0000>; + reg = <0x0 0x2000000 0x0 0x10000>; u-boot,dm-spl; }; prci: clock-controller@10000000 { |