diff options
| author | Camelia Groza <camelia.groza@nxp.com> | 2021-07-29 19:31:20 +0300 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2021-08-18 15:55:15 +0530 |
| commit | 6466b95e7c94a48d8f8093b0a765fd51ab6e84ae (patch) | |
| tree | a2ec9523a1b5d34796799a35031ec4293c2f4112 | |
| parent | 00ac37a9bc3da4e072fc1c4b460ec28c8dcd2275 (diff) | |
| download | u-boot-6466b95e7c94a48d8f8093b0a765fd51ab6e84ae.tar.gz | |
board: freescale: t208xrdb: enable Power-On Reset for rev D boards
Starting with board revision D, the MISCCSR CPLD register needs to be
configured to enable Power-on Reset for software reset commands.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | board/freescale/t208xrdb/cpld.h | 4 | ||||
| -rw-r--r-- | board/freescale/t208xrdb/t208xrdb.c | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index a623b1811f..3139c2b85f 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor + * Copyright 2021 NXP */ /* @@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value); /* RSTCON Register */ #define CPLD_RSTCON_EDC_RST 0x04 + +/* MISCCSR Register */ +#define CPLD_MISC_POR_EN 0x30 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1f0cdee0b8..947dd6aa9f 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -128,6 +128,13 @@ int misc_init_r(void) reg |= CPLD_RSTCON_EDC_RST; CPLD_WRITE(reset_ctl, reg); + /* Enable POR for boards revisions D and up */ + if (get_hw_revision() >= 'D') { + reg = CPLD_READ(misc_csr); + reg |= CPLD_MISC_POR_EN; + CPLD_WRITE(misc_csr, reg); + } + return 0; } |