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authorMario Six <mario.six@gdsys.cc>2018-10-04 09:00:54 +0200
committerSimon Glass <sjg@chromium.org>2018-11-14 09:16:27 -0800
commitc0a2b086b22b4af3253e4e22d5a9d1e809fd1352 (patch)
treeba1587a5a08c55b2afc31dd0175bca0ba26a60b9 /Documentation/devicetree/bindings
parent313d4cc3e982c6bf45e8bcf54a7db256eef41837 (diff)
downloadu-boot-c0a2b086b22b4af3253e4e22d5a9d1e809fd1352.tar.gz
misc: Add gdsys_soc driver
This patch adds a driver for the bus associated with a IHS FPGA. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/misc/gdsys,soc.txt16
1 files changed, 16 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
new file mode 100644
index 0000000000..278e935b16
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
@@ -0,0 +1,16 @@
+gdsys soc bus driver
+
+This driver provides a simple interface for the busses associated with gdsys
+IHS FPGAs. The bus itself contains devices whose register maps are contained
+within the FPGA's register space.
+
+Required properties:
+- fpga: A phandle to the controlling IHS FPGA
+
+Example:
+
+FPGA0BUS: fpga0bus {
+ compatible = "gdsys,soc";
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+};