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authorChristophe Leroy <christophe.leroy@c-s.fr>2017-07-06 10:33:21 +0200
committerTom Rini <trini@konsulko.com>2017-07-08 15:56:01 -0400
commitb1e41d1ceedf0fe90c7873bf9dfddd3690ccc11d (patch)
tree61ad7f01c98282d46798a98028cb9d476a20cfba /README
parent6f65e75a8a80e6317729f232f135ca2cc5b99d4e (diff)
downloadu-boot-b1e41d1ceedf0fe90c7873bf9dfddd3690ccc11d.tar.gz
powerpc, 8xx: Migrate to Kconfig
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'README')
-rw-r--r--README15
1 files changed, 0 insertions, 15 deletions
diff --git a/README b/README
index da9d4726c8..a6cf9d9cff 100644
--- a/README
+++ b/README
@@ -324,9 +324,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family
-- 8xx CPU Options: (if using an MPC8xx CPU)
- CONFIG_8xx_GCLK_FREQ - CPU clock
-
- 85xx CPU Options:
CONFIG_SYS_PPC64
@@ -3989,16 +3986,6 @@ Low Level (hardware related) configuration options:
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR: System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4007,8 +3994,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
-- CONFIG_SYS_DER: Debug Event Register (37-47)
-
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,