diff options
author | Tom Rini <trini@ti.com> | 2012-07-24 14:55:38 -0700 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:12 +0200 |
commit | ff7ec0f945d16dcd8fcb4b5347dca2770ac6cea4 (patch) | |
tree | 7d205e21a7c377231440f23501ff3538107f3540 /arch/arm/cpu/armv7/am33xx/ddr.c | |
parent | 87a1acbb6991521af2a8d1f75c2adacbece9ab5e (diff) | |
download | u-boot-ff7ec0f945d16dcd8fcb4b5347dca2770ac6cea4.tar.gz |
am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/ddr.c')
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 7ac144a981..993f3da007 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -42,33 +42,33 @@ static struct ddr_cmdtctrl *ioctrl_reg = { /** * Configure SDRAM */ -void config_sdram(struct sdram_config *cfg) +void config_sdram(const struct emif_regs *regs) { - writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl); - writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw); - writel(cfg->sdrcr, &emif_reg->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg->emif_sdram_config); } /** * Set SDRAM timings */ -void set_sdram_timings(struct sdram_timing *t) +void set_sdram_timings(const struct emif_regs *regs) { - writel(t->time1, &emif_reg->emif_sdram_tim_1); - writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw); - writel(t->time2, &emif_reg->emif_sdram_tim_2); - writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw); - writel(t->time3, &emif_reg->emif_sdram_tim_3); - writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw); + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw); } /** * Configure DDR PHY */ -void config_ddr_phy(struct ddr_phy_control *p) +void config_ddr_phy(const struct emif_regs *regs) { - writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1); - writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw); } /** |