imx: reorganize IMX code as other SOCs

Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

5 files changed, 0 insertions, 1581 deletions

diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig
deleted file mode 100644
index ef37c351d0..0000000000
--- a/arch/arm/cpu/armv7/mx5/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-if ARCH_MX5
-
-config MX5
-	bool
-	default y
-
-config MX51
-	bool
-
-config MX53
-	bool
-
-choice
-	prompt "MX5 board select"
-	optional
-
-config TARGET_M53EVK
-	bool "Support m53evk"
-	select MX53
-	select SUPPORT_SPL
-
-config TARGET_MX51EVK
-	bool "Support mx51evk"
-	select BOARD_LATE_INIT
-	select MX51
-
-config TARGET_MX53ARD
-	bool "Support mx53ard"
-	select MX53
-
-config TARGET_MX53CX9020
-	bool "Support CX9020"
-	select BOARD_LATE_INIT
-	select MX53
-	select DM
-	select DM_SERIAL
-
-config TARGET_MX53EVK
-	bool "Support mx53evk"
-	select BOARD_LATE_INIT
-	select MX53
-
-config TARGET_MX53LOCO
-	bool "Support mx53loco"
-	select BOARD_LATE_INIT
-	select MX53
-
-config TARGET_MX53SMD
-	bool "Support mx53smd"
-	select MX53
-
-config TARGET_TS4800
-	bool "Support TS4800"
-	select MX51
-	select SYS_FSL_ERRATUM_ESDHC_A001
-
-config TARGET_USBARMORY
-	bool "Support USB armory"
-	select MX53
-
-endchoice
-
-config SYS_SOC
-	default "mx5"
-
-source "board/aries/m53evk/Kconfig"
-source "board/beckhoff/mx53cx9020/Kconfig"
-source "board/freescale/mx51evk/Kconfig"
-source "board/freescale/mx53ard/Kconfig"
-source "board/freescale/mx53evk/Kconfig"
-source "board/freescale/mx53loco/Kconfig"
-source "board/freescale/mx53smd/Kconfig"
-source "board/inversepath/usbarmory/Kconfig"
-source "board/technologic/ts4800/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
deleted file mode 100644
index d021842f68..0000000000
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y := soc.o clock.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
deleted file mode 100644
index 610098c175..0000000000
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ /dev/null
@@ -1,949 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <div64.h>
-#include <asm/arch/sys_proto.h>
-
-enum pll_clocks {
-	PLL1_CLOCK = 0,
-	PLL2_CLOCK,
-	PLL3_CLOCK,
-#ifdef CONFIG_MX53
-	PLL4_CLOCK,
-#endif
-	PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
-	[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
-	[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
-	[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-#ifdef	CONFIG_MX53
-	[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
-#endif
-};
-
-#define AHB_CLK_ROOT    133333333
-#define SZ_DEC_1M       1000000
-#define PLL_PD_MAX      16      /* Actual pd+1 */
-#define PLL_MFI_MAX     15
-#define PLL_MFI_MIN     5
-#define ARM_DIV_MAX     8
-#define IPG_DIV_MAX     4
-#define AHB_DIV_MAX     8
-#define EMI_DIV_MAX     8
-#define NFC_DIV_MAX     8
-
-#define MX5_CBCMR	0x00015154
-#define MX5_CBCDR	0x02888945
-
-struct fixed_pll_mfd {
-	u32 ref_clk_hz;
-	u32 mfd;
-};
-
-const struct fixed_pll_mfd fixed_mfd[] = {
-	{MXC_HCLK, 24 * 16},
-};
-
-struct pll_param {
-	u32 pd;
-	u32 mfi;
-	u32 mfn;
-	u32 mfd;
-};
-
-#define PLL_FREQ_MAX(ref_clk)  (4 * (ref_clk) * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(ref_clk) \
-		((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK     420000000
-#define NFC_CLK_MAX     34000000
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-void set_usboh3_clk(void)
-{
-	clrsetbits_le32(&mxc_ccm->cscmr1,
-			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
-			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
-	clrsetbits_le32(&mxc_ccm->cscdr1,
-			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
-			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
-			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
-			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
-}
-
-void enable_usboh3_clk(bool enable)
-{
-	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
-	clrsetbits_le32(&mxc_ccm->CCGR2,
-			MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR2_USBOH3_60M(cg));
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
-	u32 mask;
-
-#if defined(CONFIG_MX51)
-	if (i2c_num > 1)
-#elif defined(CONFIG_MX53)
-	if (i2c_num > 2)
-#endif
-		return -EINVAL;
-	mask = MXC_CCM_CCGR_CG_MASK <<
-			(MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
-	if (enable)
-		setbits_le32(&mxc_ccm->CCGR1, mask);
-	else
-		clrbits_le32(&mxc_ccm->CCGR1, mask);
-	return 0;
-}
-#endif
-
-void set_usb_phy_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
-#if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(bool enable)
-{
-	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
-	clrsetbits_le32(&mxc_ccm->CCGR2,
-			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR2_USB_PHY(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
-	/* i.MX51 has a single USB PHY clock, so do nothing here. */
-}
-#elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(bool enable)
-{
-	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
-	clrsetbits_le32(&mxc_ccm->CCGR4,
-			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR4_USB_PHY1(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
-	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
-	clrsetbits_le32(&mxc_ccm->CCGR4,
-			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR4_USB_PHY2(cg));
-}
-#endif
-
-/*
- * Calculate the frequency of PLLn.
- */
-static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
-{
-	uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
-	uint64_t refclk, temp;
-	int32_t mfn_abs;
-
-	ctrl = readl(&pll->ctrl);
-
-	if (ctrl & MXC_DPLLC_CTL_HFSM) {
-		mfn = readl(&pll->hfs_mfn);
-		mfd = readl(&pll->hfs_mfd);
-		op = readl(&pll->hfs_op);
-	} else {
-		mfn = readl(&pll->mfn);
-		mfd = readl(&pll->mfd);
-		op = readl(&pll->op);
-	}
-
-	mfd &= MXC_DPLLC_MFD_MFD_MASK;
-	mfn &= MXC_DPLLC_MFN_MFN_MASK;
-	pdf = op & MXC_DPLLC_OP_PDF_MASK;
-	mfi = MXC_DPLLC_OP_MFI_RD(op);
-
-	/* 21.2.3 */
-	if (mfi < 5)
-		mfi = 5;
-
-	/* Sign extend */
-	if (mfn >= 0x04000000) {
-		mfn |= 0xfc000000;
-		mfn_abs = -mfn;
-	} else
-		mfn_abs = mfn;
-
-	refclk = infreq * 2;
-	if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
-		refclk *= 2;
-
-	do_div(refclk, pdf + 1);
-	temp = refclk * mfn_abs;
-	do_div(temp, mfd + 1);
-	ret = refclk * mfi;
-
-	if ((int)mfn < 0)
-		ret -= temp;
-	else
-		ret += temp;
-
-	return ret;
-}
-
-#ifdef CONFIG_MX51
-/*
- * This function returns the Frequency Pre-Multiplier clock.
- */
-static u32 get_fpm(void)
-{
-	u32 mult;
-	u32 ccr = readl(&mxc_ccm->ccr);
-
-	if (ccr & MXC_CCM_CCR_FPM_MULT)
-		mult = 1024;
-	else
-		mult = 512;
-
-	return MXC_CLK32 * mult;
-}
-#endif
-
-/*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = readl(&mxc_ccm->ccsr);
-
-	if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
-		ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
-		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-#endif
-	else
-		ret_val = MXC_HCLK;
-
-	return ret_val;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
-	u32 reg, freq;
-
-	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
-	return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-u32 get_periph_clk(void)
-{
-	u32 reg;
-
-	reg = readl(&mxc_ccm->cbcdr);
-	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-	reg = readl(&mxc_ccm->cbcmr);
-	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
-	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
-	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
-	case 2:
-		return get_lp_apm();
-	default:
-		return 0;
-	}
-	/* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
-	uint32_t freq, reg, div;
-
-	freq = get_ahb_clk();
-
-	reg = readl(&mxc_ccm->cbcdr);
-	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
-
-	return freq / div;
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
-	u32 freq, pred1, pred2, podf;
-
-	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
-		return get_ipg_clk();
-
-	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
-		freq = get_lp_apm();
-	else
-		freq = get_periph_clk();
-	podf = readl(&mxc_ccm->cbcdr);
-	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
-	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
-	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
-	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/* Get the output clock rate of a standard PLL MUX for peripherals. */
-static u32 get_standard_pll_sel_clk(u32 clk_sel)
-{
-	u32 freq = 0;
-
-	switch (clk_sel & 0x3) {
-	case 0:
-		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
-		break;
-	case 1:
-		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-		break;
-	case 2:
-		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
-		break;
-	case 3:
-		freq = get_lp_apm();
-		break;
-	}
-
-	return freq;
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
-	unsigned int clk_sel, freq, reg, pred, podf;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
-	freq = get_standard_pll_sel_clk(clk_sel);
-
-	reg = readl(&mxc_ccm->cscdr1);
-	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
-	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
-	freq /= (pred + 1) * (podf + 1);
-
-	return freq;
-}
-
-/*
- * get cspi clock rate.
- */
-static u32 imx_get_cspiclk(void)
-{
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
-	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
-
-	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
-	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
-	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
-	freq = get_standard_pll_sel_clk(clk_sel);
-	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
-	return ret_val;
-}
-
-/*
- * get esdhc clock rate.
- */
-static u32 get_esdhc_clk(u32 port)
-{
-	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
-	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
-	u32 cscdr1 = readl(&mxc_ccm->cscdr1);
-
-	switch (port) {
-	case 0:
-		clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
-		pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
-		podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
-		break;
-	case 1:
-		clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
-		pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
-		podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
-		break;
-	case 2:
-		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
-			return get_esdhc_clk(1);
-		else
-			return get_esdhc_clk(0);
-	case 3:
-		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
-			return get_esdhc_clk(1);
-		else
-			return get_esdhc_clk(0);
-	default:
-		break;
-	}
-
-	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
-	return freq;
-}
-
-static u32 get_axi_a_clk(void)
-{
-	u32 cbcdr = readl(&mxc_ccm->cbcdr);
-	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
-
-	return  get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_axi_b_clk(void)
-{
-	u32 cbcdr = readl(&mxc_ccm->cbcdr);
-	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
-
-	return  get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_emi_slow_clk(void)
-{
-	u32 cbcdr = readl(&mxc_ccm->cbcdr);
-	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
-	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
-
-	if (emi_clk_sel)
-		return  get_ahb_clk() / (pdf + 1);
-
-	return  get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_ddr_clk(void)
-{
-	u32 ret_val = 0;
-	u32 cbcmr = readl(&mxc_ccm->cbcmr);
-	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
-#ifdef CONFIG_MX51
-	u32 cbcdr = readl(&mxc_ccm->cbcdr);
-	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
-		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
-
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
-		ret_val /= ddr_clk_podf + 1;
-
-		return ret_val;
-	}
-#endif
-	switch (ddr_clk_sel) {
-	case 0:
-		ret_val = get_axi_a_clk();
-		break;
-	case 1:
-		ret_val = get_axi_b_clk();
-		break;
-	case 2:
-		ret_val = get_emi_slow_clk();
-		break;
-	case 3:
-		ret_val = get_ahb_clk();
-		break;
-	default:
-		break;
-	}
-
-	return ret_val;
-}
-
-/*
- * The API of get mxc clocks.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return get_mcu_main_clk();
-	case MXC_AHB_CLK:
-		return get_ahb_clk();
-	case MXC_IPG_CLK:
-		return get_ipg_clk();
-	case MXC_IPG_PERCLK:
-	case MXC_I2C_CLK:
-		return get_ipg_per_clk();
-	case MXC_UART_CLK:
-		return get_uart_clk();
-	case MXC_CSPI_CLK:
-		return imx_get_cspiclk();
-	case MXC_ESDHC_CLK:
-		return get_esdhc_clk(0);
-	case MXC_ESDHC2_CLK:
-		return get_esdhc_clk(1);
-	case MXC_ESDHC3_CLK:
-		return get_esdhc_clk(2);
-	case MXC_ESDHC4_CLK:
-		return get_esdhc_clk(3);
-	case MXC_FEC_CLK:
-		return get_ipg_clk();
-	case MXC_SATA_CLK:
-		return get_ahb_clk();
-	case MXC_DDR_CLK:
-		return get_ddr_clk();
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-u32 imx_get_uartclk(void)
-{
-	return get_uart_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
-	return get_ipg_clk();
-}
-
-static int gcd(int m, int n)
-{
-	int t;
-	while (m > 0) {
-		if (n > m) {
-			t = m;
-			m = n;
-			n = t;
-		} /* swap */
-		m -= n;
-	}
-	return n;
-}
-
-/*
- * This is to calculate various parameters based on reference clock and
- * targeted clock based on the equation:
- *      t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- * This calculation is based on a fixed MFD value for simplicity.
- */
-static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
-{
-	u64 pd, mfi = 1, mfn, mfd, t1;
-	u32 n_target = target;
-	u32 n_ref = ref, i;
-
-	/*
-	 * Make sure targeted freq is in the valid range.
-	 * Otherwise the following calculation might be wrong!!!
-	 */
-	if (n_target < PLL_FREQ_MIN(ref) ||
-		n_target > PLL_FREQ_MAX(ref)) {
-		printf("Targeted peripheral clock should be"
-			"within [%d - %d]\n",
-			PLL_FREQ_MIN(ref) / SZ_DEC_1M,
-			PLL_FREQ_MAX(ref) / SZ_DEC_1M);
-		return -EINVAL;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
-		if (fixed_mfd[i].ref_clk_hz == ref) {
-			mfd = fixed_mfd[i].mfd;
-			break;
-		}
-	}
-
-	if (i == ARRAY_SIZE(fixed_mfd))
-		return -EINVAL;
-
-	/* Use n_target and n_ref to avoid overflow */
-	for (pd = 1; pd <= PLL_PD_MAX; pd++) {
-		t1 = n_target * pd;
-		do_div(t1, (4 * n_ref));
-		mfi = t1;
-		if (mfi > PLL_MFI_MAX)
-			return -EINVAL;
-		else if (mfi < 5)
-			continue;
-		break;
-	}
-	/*
-	 * Now got pd and mfi already
-	 *
-	 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
-	 */
-	t1 = n_target * pd;
-	do_div(t1, 4);
-	t1 -= n_ref * mfi;
-	t1 *= mfd;
-	do_div(t1, n_ref);
-	mfn = t1;
-	debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
-		ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
-	i = 1;
-	if (mfn != 0)
-		i = gcd(mfd, mfn);
-	pll->pd = (u32)pd;
-	pll->mfi = (u32)mfi;
-	do_div(mfn, i);
-	pll->mfn = (u32)mfn;
-	do_div(mfd, i);
-	pll->mfd = (u32)mfd;
-
-	return 0;
-}
-
-#define calc_div(tgt_clk, src_clk, limit) ({		\
-		u32 v = 0;				\
-		if (((src_clk) % (tgt_clk)) <= 100)	\
-			v = (src_clk) / (tgt_clk);	\
-		else					\
-			v = ((src_clk) / (tgt_clk)) + 1;\
-		if (v > limit)				\
-			v = limit;			\
-		(v - 1);				\
-	})
-
-#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
-	{	\
-		writel(0x1232, &pll->ctrl);		\
-		writel(0x2, &pll->config);		\
-		writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->op);			\
-		writel(fn, &(pll->mfn));		\
-		writel((fd) - 1, &pll->mfd);		\
-		writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->hfs_op);			\
-		writel(fn, &pll->hfs_mfn);		\
-		writel((fd) - 1, &pll->hfs_mfd);	\
-		writel(0x1232, &pll->ctrl);		\
-		while (!readl(&pll->ctrl) & 0x1)	\
-			;\
-	}
-
-static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
-{
-	u32 ccsr = readl(&mxc_ccm->ccsr);
-	struct mxc_pll_reg *pll = mxc_plls[index];
-
-	switch (index) {
-	case PLL1_CLOCK:
-		/* Switch ARM to PLL2 clock */
-		writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
-					pll_param->mfi, pll_param->mfn,
-					pll_param->mfd);
-		/* Switch back */
-		writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		break;
-	case PLL2_CLOCK:
-		/* Switch to pll2 bypass clock */
-		writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
-					pll_param->mfi, pll_param->mfn,
-					pll_param->mfd);
-		/* Switch back */
-		writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		break;
-	case PLL3_CLOCK:
-		/* Switch to pll3 bypass clock */
-		writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
-					pll_param->mfi, pll_param->mfn,
-					pll_param->mfd);
-		/* Switch back */
-		writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		break;
-#ifdef CONFIG_MX53
-	case PLL4_CLOCK:
-		/* Switch to pll4 bypass clock */
-		writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
-					pll_param->mfi, pll_param->mfn,
-					pll_param->mfd);
-		/* Switch back */
-		writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
-				&mxc_ccm->ccsr);
-		break;
-#endif
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/* Config CPU clock */
-static int config_core_clk(u32 ref, u32 freq)
-{
-	int ret = 0;
-	struct pll_param pll_param;
-
-	memset(&pll_param, 0, sizeof(struct pll_param));
-
-	/* The case that periph uses PLL1 is not considered here */
-	ret = calc_pll_params(ref, freq, &pll_param);
-	if (ret != 0) {
-		printf("Error:Can't find pll parameters: %d\n", ret);
-		return ret;
-	}
-
-	return config_pll_clk(PLL1_CLOCK, &pll_param);
-}
-
-static int config_nfc_clk(u32 nfc_clk)
-{
-	u32 parent_rate = get_emi_slow_clk();
-	u32 div;
-
-	if (nfc_clk == 0)
-		return -EINVAL;
-	div = parent_rate / nfc_clk;
-	if (div == 0)
-		div++;
-	if (parent_rate / div > NFC_CLK_MAX)
-		div++;
-	clrsetbits_le32(&mxc_ccm->cbcdr,
-			MXC_CCM_CBCDR_NFC_PODF_MASK,
-			MXC_CCM_CBCDR_NFC_PODF(div - 1));
-	while (readl(&mxc_ccm->cdhipr) != 0)
-		;
-	return 0;
-}
-
-void enable_nfc_clk(unsigned char enable)
-{
-	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
-	clrsetbits_le32(&mxc_ccm->CCGR5,
-		MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
-		MXC_CCM_CCGR5_EMI_ENFC(cg));
-}
-
-#ifdef CONFIG_FSL_IIM
-void enable_efuse_prog_supply(bool enable)
-{
-	if (enable)
-		setbits_le32(&mxc_ccm->cgpr,
-			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
-	else
-		clrbits_le32(&mxc_ccm->cgpr,
-			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
-}
-#endif
-
-/* Config main_bus_clock for periphs */
-static int config_periph_clk(u32 ref, u32 freq)
-{
-	int ret = 0;
-	struct pll_param pll_param;
-
-	memset(&pll_param, 0, sizeof(struct pll_param));
-
-	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
-		ret = calc_pll_params(ref, freq, &pll_param);
-		if (ret != 0) {
-			printf("Error:Can't find pll parameters: %d\n",
-				ret);
-			return ret;
-		}
-		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
-				readl(&mxc_ccm->cbcmr))) {
-		case 0:
-			return config_pll_clk(PLL1_CLOCK, &pll_param);
-			break;
-		case 1:
-			return config_pll_clk(PLL3_CLOCK, &pll_param);
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-static int config_ddr_clk(u32 emi_clk)
-{
-	u32 clk_src;
-	s32 shift = 0, clk_sel, div = 1;
-	u32 cbcmr = readl(&mxc_ccm->cbcmr);
-
-	if (emi_clk > MAX_DDR_CLK) {
-		printf("Warning:DDR clock should not exceed %d MHz\n",
-			MAX_DDR_CLK / SZ_DEC_1M);
-		emi_clk = MAX_DDR_CLK;
-	}
-
-	clk_src = get_periph_clk();
-	/* Find DDR clock input */
-	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
-	switch (clk_sel) {
-	case 0:
-		shift = 16;
-		break;
-	case 1:
-		shift = 19;
-		break;
-	case 2:
-		shift = 22;
-		break;
-	case 3:
-		shift = 10;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if ((clk_src % emi_clk) < 10000000)
-		div = clk_src / emi_clk;
-	else
-		div = (clk_src / emi_clk) + 1;
-	if (div > 8)
-		div = 8;
-
-	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
-	while (readl(&mxc_ccm->cdhipr) != 0)
-		;
-	writel(0x0, &mxc_ccm->ccdr);
-
-	return 0;
-}
-
-/*
- * This function assumes the expected core clock has to be changed by
- * modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
- * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
- * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
- * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
- * it sets the register based on these values along with the dividers.
- * Note 1) There is no value checking for the passed-in divider values
- *         so the caller has to make sure those values are sensible.
- *      2) Also adjust the NFC divider such that the NFC clock doesn't
- *         exceed NFC_CLK_MAX.
- *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
- *         177MHz for higher voltage, this function fixes the max to 133MHz.
- *      4) This function should not have allowed diag_printf() calls since
- *         the serial driver has been stoped. But leave then here to allow
- *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- */
-int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
-{
-	freq *= SZ_DEC_1M;
-
-	switch (clk) {
-	case MXC_ARM_CLK:
-		if (config_core_clk(ref, freq))
-			return -EINVAL;
-		break;
-	case MXC_PERIPH_CLK:
-		if (config_periph_clk(ref, freq))
-			return -EINVAL;
-		break;
-	case MXC_DDR_CLK:
-		if (config_ddr_clk(freq))
-			return -EINVAL;
-		break;
-	case MXC_NFC_CLK:
-		if (config_nfc_clk(freq))
-			return -EINVAL;
-		break;
-	default:
-		printf("Warning:Unsupported or invalid clock type\n");
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_MX53
-/*
- * The clock for the external interface can be set to use internal clock
- * if fuse bank 4, row 3, bit 2 is set.
- * This is an undocumented feature and it was confirmed by Freescale's support:
- * Fuses (but not pins) may be used to configure SATA clocks.
- * Particularly the i.MX53 Fuse_Map contains the next information
- * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
- * '00' - 100MHz (External)
- * '01' - 50MHz (External)
- * '10' - 120MHz, internal (USB PHY)
- * '11' - Reserved
-*/
-void mxc_set_sata_internal_clock(void)
-{
-	u32 *tmp_base =
-		(u32 *)(IIM_BASE_ADDR + 0x180c);
-
-	set_usb_phy_clk();
-
-	clrsetbits_le32(tmp_base, 0x6, 0x4);
-}
-#endif
-
-/*
- * Dump some core clockes.
- */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 freq;
-
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
-	printf("PLL1       %8d MHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-	printf("PLL2       %8d MHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
-	printf("PLL3       %8d MHz\n", freq / 1000000);
-#ifdef	CONFIG_MX53
-	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-	printf("PLL4       %8d MHz\n", freq / 1000000);
-#endif
-
-	printf("\n");
-	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
-	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
-	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
-	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
-	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
-	return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
-	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
-	"display clocks",
-	""
-);
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
deleted file mode 100644
index f5bc6728b7..0000000000
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <linux/linkage.h>
-
-.section ".text.init", "x"
-
-.macro init_arm_erratum
-	/* ARM erratum ID #468414 */
-	mrc 15, 0, r1, c1, c0, 1
-	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
-	mcr 15, 0, r1, c1, c0, 1
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
-	/* explicitly disable L2 cache */
-	mrc 15, 0, r0, c1, c0, 1
-	bic r0, r0, #0x2
-	mcr 15, 0, r0, c1, c0, 1
-
-	/* reconfigure L2 cache aux control reg */
-	ldr r0, =0xC0 |			/* tag RAM */ \
-		 0x4 |			/* data RAM */ \
-		 1 << 24 |		/* disable write allocate delay */ \
-		 1 << 23 |		/* disable write allocate combine */ \
-		 1 << 22		/* disable write allocate */
-
-#if defined(CONFIG_MX51)
-	ldr r3, [r4, #ROM_SI_REV]
-	cmp r3, #0x10
-
-	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #1 << 25
-#endif
-
-	mcr 15, 1, r0, c9, c0, 2
-
-	/* enable L2 cache */
-	mrc 15, 0, r0, c1, c0, 1
-	orr r0, r0, #2
-	mcr 15, 0, r0, c1, c0, 1
-
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	ldr r0, =AIPS1_BASE_ADDR
-	ldr r1, =0x77777777
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	ldr r0, =AIPS2_BASE_ADDR
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
-#ifdef CONFIG_MX51
-	/* VPU and IPU given higher priority (0x4)
-	 * IPU accesses with ID=0x1 given highest priority (=0xA)
-	 */
-	ldr r0, =M4IF_BASE_ADDR
-
-	ldr r1, =0x00000203
-	str r1, [r0, #0x40]
-
-	str r4, [r0, #0x44]
-
-	ldr r1, =0x00120125
-	str r1, [r0, #0x9C]
-
-	ldr r1, =0x001901A3
-	str r1, [r0, #0x48]
-
-#endif
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
-	ldr r0, =\pll
-	adr r2, W_DP_\freq
-	bl setup_pll_func
-.endm
-
-#define W_DP_OP		0
-#define W_DP_MFD	4
-#define W_DP_MFN	8
-
-setup_pll_func:
-	ldr r1, =0x00001232
-	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
-	mov r1, #0x2
-	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
-	ldr r1, [r2, #W_DP_OP]
-	str r1, [r0, #PLL_DP_OP]
-	str r1, [r0, #PLL_DP_HFS_OP]
-
-	ldr r1, [r2, #W_DP_MFD]
-	str r1, [r0, #PLL_DP_MFD]
-	str r1, [r0, #PLL_DP_HFS_MFD]
-
-	ldr r1, [r2, #W_DP_MFN]
-	str r1, [r0, #PLL_DP_MFN]
-	str r1, [r0, #PLL_DP_HFS_MFN]
-
-	ldr r1, =0x00001232
-	str r1, [r0, #PLL_DP_CTL]
-1:	ldr r1, [r0, #PLL_DP_CTL]
-	ands r1, r1, #0x1
-	beq 1b
-
-	/* r10 saved upper lr */
-	mov pc, lr
-
-.macro setup_pll_errata pll, freq
-	ldr r2, =\pll
-	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
-	ldr r1, =0x00001236
-	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
-1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
-	ands r1, r1, #0x1
-	beq 1b
-
-	ldr r5, \freq
-	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
-	str r5, [r2, #PLL_DP_HFS_MFN]
-
-	mov r1, #0x1
-	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
-
-2:	ldr r1, [r2, #PLL_DP_CONFIG]
-	tst r1, #1
-	bne 2b
-
-	ldr r1, =100		     /* Wait at least 4 us */
-3:	subs r1, r1, #1
-	bge 3b
-
-	mov r1, #0x2
-	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-.endm
-
-.macro init_clock
-#if defined (CONFIG_MX51)
-	ldr r0, =CCM_BASE_ADDR
-
-	/* Gate of clocks to the peripherals first */
-	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r4, [r0, #CLKCTL_CCGR1]
-	str r4, [r0, #CLKCTL_CCGR2]
-	str r4, [r0, #CLKCTL_CCGR3]
-
-	ldr r1, =0x00030000
-	str r1, [r0, #CLKCTL_CCGR4]
-	ldr r1, =0x00FFF030
-	str r1, [r0, #CLKCTL_CCGR5]
-	ldr r1, =0x00000300
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Disable IPU and HSC dividers */
-	mov r1, #0x60000
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* Make sure to switch the DDR away from PLL 1 */
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	/* Switch ARM to step clock */
-	mov r1, #0x4
-	str r1, [r0, #CLKCTL_CCSR]
-
-#if defined(CONFIG_MX51_PLL_ERRATA)
-	setup_pll PLL1_BASE_ADDR, 864
-	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
-#else
-	setup_pll PLL1_BASE_ADDR, 800
-#endif
-
-	setup_pll PLL3_BASE_ADDR, 665
-
-	/* Switch peripheral to PLL 3 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	ldr r1, =0x13239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	setup_pll PLL2_BASE_ADDR, 665
-
-	/* Switch peripheral to PLL2 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-
-	setup_pll PLL3_BASE_ADDR, 216
-
-	/* Set the platform clock dividers */
-	ldr r0, =ARM_BASE_ADDR
-	ldr r1, =0x00000725
-	str r1, [r0, #0x14]
-
-	ldr r0, =CCM_BASE_ADDR
-
-	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
-	ldr r3, [r4, #ROM_SI_REV]
-	cmp r3, #0x10
-	movls r1, #0x1
-	movhi r1, #0
-
-	str r1, [r0, #CLKCTL_CACRR]
-
-	/* Switch ARM back to PLL 1 */
-	str r4, [r0, #CLKCTL_CCSR]
-
-	/* setup the rest */
-	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
-	str r1, [r0, #CLKCTL_CBCDR]
-
-	/* Restore the default values in the Gate registers */
-	ldr r1, =0xFFFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR4]
-	str r1, [r0, #CLKCTL_CCGR5]
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Use PLL 2 for UART's, get 66.5MHz from it */
-	ldr r1, =0xA5A2A020
-	str r1, [r0, #CLKCTL_CSCMR1]
-	ldr r1, =0x00C30321
-	str r1, [r0, #CLKCTL_CSCDR1]
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	str r4, [r0, #CLKCTL_CCDR]
-
-	/* for cko - for ARM div by 8 */
-	mov r1, #0x000A0000
-	add r1, r1, #0x00000F0
-	str r1, [r0, #CLKCTL_CCOSR]
-#else	/* CONFIG_MX53 */
-	ldr r0, =CCM_BASE_ADDR
-
-	/* Gate of clocks to the peripherals first */
-	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r4, [r0, #CLKCTL_CCGR1]
-	str r4, [r0, #CLKCTL_CCGR2]
-	str r4, [r0, #CLKCTL_CCGR3]
-	str r4, [r0, #CLKCTL_CCGR7]
-	ldr r1, =0x00030000
-	str r1, [r0, #CLKCTL_CCGR4]
-	ldr r1, =0x00FFF030
-	str r1, [r0, #CLKCTL_CCGR5]
-	ldr r1, =0x0F00030F
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Switch ARM to step clock */
-	mov r1, #0x4
-	str r1, [r0, #CLKCTL_CCSR]
-
-	setup_pll PLL1_BASE_ADDR, 800
-
-	setup_pll PLL3_BASE_ADDR, 400
-
-	/* Switch peripheral to PLL3 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x00015154
-	str r1, [r0, #CLKCTL_CBCMR]
-	ldr r1, =0x02898945
-	str r1, [r0, #CLKCTL_CBCDR]
-	/* make sure change is effective */
-1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	setup_pll PLL2_BASE_ADDR, 400
-
-	/* Switch peripheral to PLL2 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x00888945
-	str r1, [r0, #CLKCTL_CBCDR]
-
-	ldr r1, =0x00016154
-	str r1, [r0, #CLKCTL_CBCMR]
-
-	/*change uart clk parent to pll2*/
-	ldr r1, [r0, #CLKCTL_CSCMR1]
-	and r1, r1, #0xfcffffff
-	orr r1, r1, #0x01000000
-	str r1, [r0, #CLKCTL_CSCMR1]
-
-	/* make sure change is effective */
-1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	setup_pll PLL3_BASE_ADDR, 216
-
-	setup_pll PLL4_BASE_ADDR, 455
-
-	/* Set the platform clock dividers */
-	ldr r0, =ARM_BASE_ADDR
-	ldr r1, =0x00000124
-	str r1, [r0, #0x14]
-
-	ldr r0, =CCM_BASE_ADDR
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CACRR]
-
-	/* Switch ARM back to PLL 1. */
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCSR]
-
-	/* make uart div=6 */
-	ldr r1, [r0, #CLKCTL_CSCDR1]
-	and r1, r1, #0xffffffc0
-	orr r1, r1, #0x0a
-	str r1, [r0, #CLKCTL_CSCDR1]
-
-	/* Restore the default values in the Gate registers */
-	ldr r1, =0xFFFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR4]
-	str r1, [r0, #CLKCTL_CCGR5]
-	str r1, [r0, #CLKCTL_CCGR6]
-	str r1, [r0, #CLKCTL_CCGR7]
-
-	mov r1, #0x00000
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* for cko - for ARM div by 8 */
-	mov r1, #0x000A0000
-	add r1, r1, #0x00000F0
-	str r1, [r0, #CLKCTL_CCOSR]
-
-#endif	/* CONFIG_MX53 */
-.endm
-
-ENTRY(lowlevel_init)
-	mov r10, lr
-	mov r4, #0	/* Fix R4 to 0 */
-
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
-	ldr r0, =GPIO1_BASE_ADDR
-	ldr r1, [r0, #0x0]
-	orr r1, r1, #1 << 23
-	str r1, [r0, #0x0]
-	ldr r1, [r0, #0x4]
-	orr r1, r1, #1 << 23
-	str r1, [r0, #0x4]
-#endif
-
-	init_arm_erratum
-
-	init_l2cc
-
-	init_aips
-
-	init_m4if
-
-	init_clock
-
-	mov pc, r10
-ENDPROC(lowlevel_init)
-
-/* Board level setting value */
-#if defined(CONFIG_MX51_PLL_ERRATA)
-W_DP_864:		.word DP_OP_864
-			.word DP_MFD_864
-			.word DP_MFN_864
-W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
-#else
-W_DP_800:		.word DP_OP_800
-			.word DP_MFD_800
-			.word DP_MFN_800
-#endif
-#if defined(CONFIG_MX51)
-W_DP_665:		.word DP_OP_665
-			.word DP_MFD_665
-			.word DP_MFN_665
-#endif
-W_DP_216:		.word DP_OP_216
-			.word DP_MFD_216
-			.word DP_MFN_216
-W_DP_400:               .word DP_OP_400
-			.word DP_MFD_400
-			.word DP_MFN_400
-W_DP_455:               .word DP_OP_455
-			.word DP_MFD_455
-			.word DP_MFN_455
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
deleted file mode 100644
index e6cc7cb9c4..0000000000
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
-
-#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
-#error "CPU_TYPE not defined"
-#endif
-
-u32 get_cpu_rev(void)
-{
-#ifdef CONFIG_MX51
-	int system_rev = 0x51000;
-#else
-	int system_rev = 0x53000;
-#endif
-	int reg = __raw_readl(ROM_SI_REV);
-
-#if defined(CONFIG_MX51)
-	switch (reg) {
-	case 0x02:
-		system_rev |= CHIP_REV_1_1;
-		break;
-	case 0x10:
-		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
-			system_rev |= CHIP_REV_2_5;
-		else
-			system_rev |= CHIP_REV_2_0;
-		break;
-	case 0x20:
-		system_rev |= CHIP_REV_3_0;
-		break;
-	default:
-		system_rev |= CHIP_REV_1_0;
-		break;
-	}
-#else
-	if (reg < 0x20)
-		system_rev |= CHIP_REV_1_0;
-	else
-		system_rev |= reg;
-#endif
-	return system_rev;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[1];
-	struct fuse_bank1_regs *fuse =
-			(struct fuse_bank1_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif
-
-#ifdef CONFIG_MX53
-void boot_mode_apply(unsigned cfg_val)
-{
-	writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
-}
-/*
- * cfg_val will be used for
- * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- *
- * If bit 28 of LPGR is set upon watchdog reset,
- * bits[25:0] of LPGR will move to SBMR.
- */
-const struct boot_mode soc_boot_modes[] = {
-	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
-	/* usb or serial download */
-	{"usb",		MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
-	{"sata",	MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
-	{"escpi1:0",	MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
-	{"escpi1:1",	MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
-	{"escpi1:2",	MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
-	{"escpi1:3",	MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
-	/* 4 bit bus width */
-	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
-	{"esdhc2",	MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
-	{"esdhc3",	MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
-	{"esdhc4",	MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
-	{NULL,		0},
-};
-#endif