diff options
| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:37 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:23 +0200 |
| commit | f40107345cbcd6e0d1747eda45e76c4e2a6df0db (patch) | |
| tree | 19926012178f2c73c3fc5c60d391d8d40f1cfaff /arch/arm/cpu/armv7/omap-common/clocks-common.c | |
| parent | 6ad8d67de8f9ec9d4a8a90b0b3f78f13bec43c89 (diff) | |
| download | u-boot-f40107345cbcd6e0d1747eda45e76c4e2a6df0db.tar.gz | |
OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common/clocks-common.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index a183c34ea3..e96a430f74 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -459,6 +459,7 @@ void freq_update_core(void) { u32 freq_config1 = 0; const struct dpll_params *core_dpll_params; + u32 omap_rev = omap_revision(); core_dpll_params = get_core_dpll_params(); /* Put EMIF clock domain in sw wakeup mode */ @@ -484,11 +485,18 @@ void freq_update_core(void) hang(); } - /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + /* + * Putting EMIF in HW_AUTO is seen to be causing issues with + * EMIF clocks and the master DLL. Put EMIF in SW_WKUP + * in OMAP5430 ES1.0 silicon + */ + if (omap_rev != OMAP5430_ES1_0) { + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + } } void bypass_dpll(u32 *const base) |