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| author | Tom Rini <trini@konsulko.com> | 2020-05-20 08:46:56 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-20 08:46:56 -0400 |
| commit | b0b13f4114d30b6756e0f6f3b5819d78de22541e (patch) | |
| tree | 5e3afc6650d3b9f6040e1d51972120eb3ee2f35e /arch/arm/dts/fsl-ls2080a-qds.dtsi | |
| parent | 023329284dadbbe7e0ed40bcda8101653997e507 (diff) | |
| parent | 13bc860727ee406f073c8176dd2d6b9dacf35443 (diff) | |
| download | u-boot-b0b13f4114d30b6756e0f6f3b5819d78de22541e.tar.gz | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/20May2020
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
Diffstat (limited to 'arch/arm/dts/fsl-ls2080a-qds.dtsi')
| -rw-r--r-- | arch/arm/dts/fsl-ls2080a-qds.dtsi | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 0000000000..cb7851f2cc --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs256s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; |