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authorTeresa Remmet <t.remmet@phytec.de>2021-01-13 16:28:09 +0100
committerStefano Babic <sbabic@denx.de>2021-01-23 11:30:32 +0100
commitc661c511e9cfc86f18b1326b0f0d1e338a8c442a (patch)
treeddfd4ea167f447ecce01c2f3fb772019778c9cba /arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
parent3f832699ff0be590422ac32e409320d684c25ab9 (diff)
downloadu-boot-c661c511e9cfc86f18b1326b0f0d1e338a8c442a.tar.gz
board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support
Add initial support PHYTEC phyCORE-i.MX8MP SOM. Supported features: - 2GB LPDDR4 RAM - eMMC - external SD - debug UART2 - watchdog Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi')
-rw-r--r--arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi114
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
new file mode 100644
index 0000000000..20e7f63ff9
--- /dev/null
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_32k {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_pins {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pmic {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};