Tegra20: Move some include files to arch-tegra for sharing with Tegra30

The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>

18 files changed, 202 insertions, 1621 deletions

diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h
deleted file mode 100644
index 70d94c5041..0000000000
--- a/arch/arm/include/asm/arch-tegra20/ap20.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY	(1000)
-
-#define NVBL_PLLP_KHZ	(216000)
-
-#define PLLX_ENABLED		(1 << 30)
-#define CCLK_BURST_POLICY	0x20008888
-#define SUPER_CCLK_DIVIDER	0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0             0x0
-
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
-
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM      0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM       0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE  0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH  0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- *       stack is placed below the AVP stack. Once the CPU stack has been moved,
- *       the AVP is free to use the IRAM the CPU stack previously occupied if
- *       it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- *       CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT	\
-	(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE	0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT	\
-	(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE	0x1000
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP			2
-#define HALT_COP_EVENT_JTAG		(1 << 28)
-#define HALT_COP_EVENT_IRQ_1		(1 << 11)
-#define HALT_COP_EVENT_FIQ_1		(1 << 9)
-
-/* This is the main entry into U-Boot, used by the Cortex-A9 */
-extern void _start(void);
-
-/**
- * Works out the SOC type used for clocks settings
- *
- * @return	SOC type - see TEGRA_SOC...
- */
-int tegra_get_chip_type(void);
diff --git a/arch/arm/include/asm/arch-tegra20/board.h b/arch/arm/include/asm/arch-tegra20/board.h
deleted file mode 100644
index a90d36c708..0000000000
--- a/arch/arm/include/asm/arch-tegra20/board.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_BOARD_H_
-#define _TEGRA_BOARD_H_
-
-/* Setup UARTs for the board according to the selected config */
-void board_init_uart_f(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/clk_rst.h b/arch/arm/include/asm/arch-tegra20/clk_rst.h
deleted file mode 100644
index 8c3be91514..0000000000
--- a/arch/arm/include/asm/arch-tegra20/clk_rst.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CLK_RST_H_
-#define _CLK_RST_H_
-
-/* PLL registers - there are several PLLs in the clock controller */
-struct clk_pll {
-	uint pll_base;		/* the control register */
-	uint pll_out;		/* output control */
-	uint reserved;
-	uint pll_misc;		/* other misc things */
-};
-
-/* PLL registers - there are several PLLs in the clock controller */
-struct clk_pll_simple {
-	uint pll_base;		/* the control register */
-	uint pll_misc;		/* other misc things */
-};
-
-/*
- * Most PLLs use the clk_pll structure, but some have a simpler two-member
- * structure for which we use clk_pll_simple. The reason for this non-
- * othogonal setup is not stated.
- */
-enum {
-	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
-	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
-	TEGRA_CLK_REGS		= 3,	/* Number of clock enable registers */
-	TEGRA_CLK_SOURCES	= 64,	/* Number of peripheral clock sources */
-};
-
-/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-struct clk_rst_ctlr {
-	uint crc_rst_src;			/* _RST_SOURCE_0,0x00 */
-	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
-	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
-	uint crc_reserved0;		/* reserved_0,		0x1C */
-	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
-	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
-	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
-	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
-	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
-	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
-	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
-	uint crc_reserved1;		/* reserved_1,		0x3C */
-	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
-	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
-	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
-	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
-	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
-	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
-	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
-	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
-	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
-
-	struct clk_pll crc_pll[TEGRA_CLK_PLLS];	/* PLLs from 0x80 to 0xdc */
-
-	/* PLLs from 0xe0 to 0xf4    */
-	struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
-
-	uint crc_reserved10;		/* _reserved_10,	0xF8 */
-	uint crc_reserved11;		/* _reserved_11,	0xFC */
-
-	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
-	uint crc_reserved20[80];	/*			0x200-33C */
-	uint crc_cpu_cmplx_set;		/* _CPU_CMPLX_SET_0,	0x340	  */
-	uint crc_cpu_cmplx_clr;		/* _CPU_CMPLX_CLR_0,	0x344     */
-};
-
-/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
-#define CPU1_CLK_STP_SHIFT	9
-
-#define CPU0_CLK_STP_SHIFT	8
-#define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
-
-/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
-#define PLL_BYPASS_SHIFT	31
-#define PLL_BYPASS_MASK		(1U << PLL_BYPASS_SHIFT)
-
-#define PLL_ENABLE_SHIFT	30
-#define PLL_ENABLE_MASK		(1U << PLL_ENABLE_SHIFT)
-
-#define PLL_BASE_OVRRIDE_MASK	(1U << 28)
-
-#define PLL_DIVP_SHIFT		20
-#define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
-
-#define PLL_DIVN_SHIFT		8
-#define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
-
-#define PLL_DIVM_SHIFT		0
-#define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
-
-/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
-#define PLL_CPCON_SHIFT		8
-#define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
-
-#define PLL_LFCON_SHIFT		4
-#define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
-
-#define PLLU_VCO_FREQ_SHIFT	20
-#define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
-
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT		30
-#define OSC_FREQ_MASK		(3U << OSC_FREQ_SHIFT)
-#define OSC_XOBP_SHIFT		1
-#define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
-
-/*
- * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
- * but can be 16. We could use knowledge we have to restrict the mask in
- * the 8-bit cases (the divider_bits value returned by
- * get_periph_clock_source()) but it does not seem worth it since the code
- * already checks the ranges of values it is writing, in clk_get_divider().
- */
-#define OUT_CLK_DIVISOR_SHIFT	0
-#define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
-
-#define OUT_CLK_SOURCE_SHIFT	30
-#define OUT_CLK_SOURCE_MASK	(3U << OUT_CLK_SOURCE_SHIFT)
-
-#define OUT_CLK_SOURCE4_SHIFT	28
-#define OUT_CLK_SOURCE4_MASK	(15U << OUT_CLK_SOURCE4_SHIFT)
-
-#endif	/* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
new file mode 100644
index 0000000000..089b3e7bfa
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra20 clock PLL tables */
+
+#ifndef _CLOCK_TABLES_H_
+#define _CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of clocks */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_RESERVED1,
+	PERIPH_ID_RESERVED2,
+	PERIPH_ID_AC97,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TWC,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_IDE,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_RESERVED30,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_RESERVED74,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_RESERVED79,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_RESERVED81,
+	PERIPH_ID_RESERVED82,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+		(id) < CLOCK_ID_FIRST_SIMPLE)
+
+#endif	/* _CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
index ff83bbf293..f592b9550e 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -19,389 +19,11 @@
  * MA 02111-1307 USA
  */
 
-/* Tegra2 clock control functions */
+/* Tegra20 clock control functions */
 
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA20_CLOCK_H
+#define _TEGRA20_CLOCK_H
 
-/* Set of oscillator frequencies supported in the internal API. */
-enum clock_osc_freq {
-	/* All in MHz, so 13_0 is 13.0MHz */
-	CLOCK_OSC_FREQ_13_0,
-	CLOCK_OSC_FREQ_19_2,
-	CLOCK_OSC_FREQ_12_0,
-	CLOCK_OSC_FREQ_26_0,
+#include <asm/arch-tegra/clock.h>
 
-	CLOCK_OSC_FREQ_COUNT,
-};
-
-/* The PLLs supported by the hardware */
-enum clock_id {
-	CLOCK_ID_FIRST,
-	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
-	CLOCK_ID_MEMORY,
-	CLOCK_ID_PERIPH,
-	CLOCK_ID_AUDIO,
-	CLOCK_ID_USB,
-	CLOCK_ID_DISPLAY,
-
-	/* now the simple ones */
-	CLOCK_ID_FIRST_SIMPLE,
-	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
-	CLOCK_ID_EPCI,
-	CLOCK_ID_SFROM32KHZ,
-
-	/* These are the base clocks (inputs to the Tegra SOC) */
-	CLOCK_ID_32KHZ,
-	CLOCK_ID_OSC,
-
-	CLOCK_ID_COUNT,	/* number of clocks */
-	CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
-	PERIPH_ID_FIRST,
-
-	/* Low word: 31:0 */
-	PERIPH_ID_CPU = PERIPH_ID_FIRST,
-	PERIPH_ID_RESERVED1,
-	PERIPH_ID_RESERVED2,
-	PERIPH_ID_AC97,
-	PERIPH_ID_RTC,
-	PERIPH_ID_TMR,
-	PERIPH_ID_UART1,
-	PERIPH_ID_UART2,
-
-	/* 8 */
-	PERIPH_ID_GPIO,
-	PERIPH_ID_SDMMC2,
-	PERIPH_ID_SPDIF,
-	PERIPH_ID_I2S1,
-	PERIPH_ID_I2C1,
-	PERIPH_ID_NDFLASH,
-	PERIPH_ID_SDMMC1,
-	PERIPH_ID_SDMMC4,
-
-	/* 16 */
-	PERIPH_ID_TWC,
-	PERIPH_ID_PWM,
-	PERIPH_ID_I2S2,
-	PERIPH_ID_EPP,
-	PERIPH_ID_VI,
-	PERIPH_ID_2D,
-	PERIPH_ID_USBD,
-	PERIPH_ID_ISP,
-
-	/* 24 */
-	PERIPH_ID_3D,
-	PERIPH_ID_IDE,
-	PERIPH_ID_DISP2,
-	PERIPH_ID_DISP1,
-	PERIPH_ID_HOST1X,
-	PERIPH_ID_VCP,
-	PERIPH_ID_RESERVED30,
-	PERIPH_ID_CACHE2,
-
-	/* Middle word: 63:32 */
-	PERIPH_ID_MEM,
-	PERIPH_ID_AHBDMA,
-	PERIPH_ID_APBDMA,
-	PERIPH_ID_RESERVED35,
-	PERIPH_ID_KBC,
-	PERIPH_ID_STAT_MON,
-	PERIPH_ID_PMC,
-	PERIPH_ID_FUSE,
-
-	/* 40 */
-	PERIPH_ID_KFUSE,
-	PERIPH_ID_SBC1,
-	PERIPH_ID_SNOR,
-	PERIPH_ID_SPI1,
-	PERIPH_ID_SBC2,
-	PERIPH_ID_XIO,
-	PERIPH_ID_SBC3,
-	PERIPH_ID_DVC_I2C,
-
-	/* 48 */
-	PERIPH_ID_DSI,
-	PERIPH_ID_TVO,
-	PERIPH_ID_MIPI,
-	PERIPH_ID_HDMI,
-	PERIPH_ID_CSI,
-	PERIPH_ID_TVDAC,
-	PERIPH_ID_I2C2,
-	PERIPH_ID_UART3,
-
-	/* 56 */
-	PERIPH_ID_RESERVED56,
-	PERIPH_ID_EMC,
-	PERIPH_ID_USB2,
-	PERIPH_ID_USB3,
-	PERIPH_ID_MPE,
-	PERIPH_ID_VDE,
-	PERIPH_ID_BSEA,
-	PERIPH_ID_BSEV,
-
-	/* Upper word 95:64 */
-	PERIPH_ID_SPEEDO,
-	PERIPH_ID_UART4,
-	PERIPH_ID_UART5,
-	PERIPH_ID_I2C3,
-	PERIPH_ID_SBC4,
-	PERIPH_ID_SDMMC3,
-	PERIPH_ID_PCIE,
-	PERIPH_ID_OWR,
-
-	/* 72 */
-	PERIPH_ID_AFI,
-	PERIPH_ID_CORESIGHT,
-	PERIPH_ID_RESERVED74,
-	PERIPH_ID_AVPUCQ,
-	PERIPH_ID_RESERVED76,
-	PERIPH_ID_RESERVED77,
-	PERIPH_ID_RESERVED78,
-	PERIPH_ID_RESERVED79,
-
-	/* 80 */
-	PERIPH_ID_RESERVED80,
-	PERIPH_ID_RESERVED81,
-	PERIPH_ID_RESERVED82,
-	PERIPH_ID_RESERVED83,
-	PERIPH_ID_IRAMA,
-	PERIPH_ID_IRAMB,
-	PERIPH_ID_IRAMC,
-	PERIPH_ID_IRAMD,
-
-	/* 88 */
-	PERIPH_ID_CRAM2,
-
-	PERIPH_ID_COUNT,
-	PERIPH_ID_NONE = -1,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
-#define PERIPH_REG(id) ((id) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range, and not a simple PLL */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
-		(id) < CLOCK_ID_FIRST_SIMPLE)
-
-/* PLL stabilization delay in usec */
-#define CLOCK_PLL_STABLE_DELAY_US 300
-
-/* return the current oscillator clock frequency */
-enum clock_osc_freq clock_get_osc_freq(void);
-
-/**
- * Start PLL using the provided configuration parameters.
- *
- * @param id	clock id
- * @param divm	input divider
- * @param divn	feedback divider
- * @param divp	post divider 2^n
- * @param cpcon	charge pump setup control
- * @param lfcon	loop filter setup control
- *
- * @returns monotonic time in us that the PLL will be stable
- */
-unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
-		u32 divp, u32 cpcon, u32 lfcon);
-
-/**
- * Read low-level parameters of a PLL.
- *
- * @param id	clock id to read (note: USB is not supported)
- * @param divm	returns input divider
- * @param divn	returns feedback divider
- * @param divp	returns post divider 2^n
- * @param cpcon	returns charge pump setup control
- * @param lfcon	returns loop filter setup control
- *
- * @returns 0 if ok, -1 on error (invalid clock id)
- */
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
-		      u32 *divp, u32 *cpcon, u32 *lfcon);
-
-/*
- * Enable a clock
- *
- * @param id	clock id
- */
-void clock_enable(enum periph_id clkid);
-
-/*
- * Disable a clock
- *
- * @param id	clock id
- */
-void clock_disable(enum periph_id clkid);
-
-/*
- * Set whether a clock is enabled or disabled.
- *
- * @param id		clock id
- * @param enable	1 to enable, 0 to disable
- */
-void clock_set_enable(enum periph_id clkid, int enable);
-
-/**
- * Reset a peripheral. This puts it in reset, waits for a delay, then takes
- * it out of reset and waits for th delay again.
- *
- * @param periph_id	peripheral to reset
- * @param us_delay	time to delay in microseconds
- */
-void reset_periph(enum periph_id periph_id, int us_delay);
-
-/**
- * Put a peripheral into or out of reset.
- *
- * @param periph_id	peripheral to reset
- * @param enable	1 to put into reset, 0 to take out of reset
- */
-void reset_set_enable(enum periph_id periph_id, int enable);
-
-
-/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
-enum crc_reset_id {
-	/* Things we can hold in reset for each CPU */
-	crc_rst_cpu = 1,
-	crc_rst_de = 1 << 2,	/* What is de? */
-	crc_rst_watchdog = 1 << 3,
-	crc_rst_debug = 1 << 4,
-};
-
-/**
- * Put parts of the CPU complex into or out of reset.\
- *
- * @param cpu		cpu number (0 or 1 on Tegra2)
- * @param which		which parts of the complex to affect (OR of crc_reset_id)
- * @param reset		1 to assert reset, 0 to de-assert
- */
-void reset_cmplx_set_enable(int cpu, int which, int reset);
-
-/**
- * Set the source for a peripheral clock. This plus the divisor sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id	peripheral to adjust
- * @param source	source clock (0, 1, 2 or 3)
- */
-void clock_ll_set_source(enum periph_id periph_id, unsigned source);
-
-/**
- * Set the source and divisor for a peripheral clock. This sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id	peripheral to adjust
- * @param source	source clock (0, 1, 2 or 3)
- * @param divisor	divisor value to use
- */
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
-		unsigned divisor);
-
-/**
- * Start a peripheral PLL clock at the given rate. This also resets the
- * peripheral.
- *
- * @param periph_id	peripheral to start
- * @param parent	PLL id of required parent clock
- * @param rate		Required clock rate in Hz
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_start_periph_pll(enum periph_id periph_id,
-		enum clock_id parent, unsigned rate);
-
-/**
- * Returns the rate of a peripheral clock in Hz. Since the caller almost
- * certainly knows the parent clock (having just set it) we require that
- * this be passed in so we don't need to work it out.
- *
- * @param periph_id	peripheral to start
- * @param parent	PLL id of parent clock (used to calculate rate, you
- *			must know this!)
- * @return clock rate of peripheral in Hz
- */
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
-		enum clock_id parent);
-
-/**
- * Adjust peripheral PLL clock to the given rate. This does not reset the
- * peripheral. If a second stage divisor is not available, pass NULL for
- * extra_div. If it is available, then this parameter will return the
- * divisor selected (which will be a power of 2 from 1 to 256).
- *
- * @param periph_id	peripheral to start
- * @param parent	PLL id of required parent clock
- * @param rate		Required clock rate in Hz
- * @param extra_div	value for the second-stage divisor (NULL if one is
-			not available)
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
-		enum clock_id parent, unsigned rate, int *extra_div);
-
-/**
- * Returns the clock rate of a specified clock, in Hz.
- *
- * @param parent	PLL id of clock to check
- * @return rate of clock in Hz
- */
-unsigned clock_get_rate(enum clock_id clkid);
-
-/**
- * Start up a UART using low-level calls
- *
- * Prior to relocation clock_start_periph_pll() cannot be called. This
- * function provides a way to set up a UART using low-level calls which
- * do not require BSS.
- *
- * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
- */
-void clock_ll_start_uart(enum periph_id periph_id);
-
-/**
- * Decode a peripheral ID from a device tree node.
- *
- * This works by looking up the peripheral's 'clocks' node and reading out
- * the second cell, which is the clock number / peripheral ID.
- *
- * @param blob		FDT blob to use
- * @param node		Node to look at
- * @return peripheral ID, or PERIPH_ID_NONE if none
- */
-enum periph_id clock_decode_periph_id(const void *blob, int node);
-
-/**
- * Checks if the oscillator bypass is enabled (XOBP bit)
- *
- * @return 1 if bypass is enabled, 0 if not
- */
-int clock_get_osc_bypass(void);
-
-/*
- * Checks that clocks are valid and prints a warning if not
- *
- * @return 0 if ok, -1 on error
- */
-int clock_verify(void);
-
-/* Initialize the clocks */
-void clock_init(void);
-
-/* Initialize the PLLs */
-void clock_early_init(void);
-
-#endif
+#endif	/* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/fuse.h b/arch/arm/include/asm/arch-tegra20/fuse.h
deleted file mode 100644
index b7e3808a4f..0000000000
--- a/arch/arm/include/asm/arch-tegra20/fuse.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _FUSE_H_
-#define _FUSE_H_
-
-/* FUSE registers */
-struct fuse_regs {
-	u32 reserved0[64];		/* 0x00 - 0xFC: */
-	u32 production_mode;		/* 0x100: FUSE_PRODUCTION_MODE */
-	u32 reserved1[3];		/* 0x104 - 0x10c: */
-	u32 sku_info;			/* 0x110 */
-	u32 reserved2[13];		/* 0x114 - 0x144: */
-	u32 fa;				/* 0x148: FUSE_FA */
-	u32 reserved3[21];		/* 0x14C - 0x19C: */
-	u32 security_mode;		/* 0x1A0: FUSE_SECURITY_MODE */
-};
-
-#endif	/* ifndef _FUSE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
index 06be4c28be..e2848fec67 100644
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -20,8 +20,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA_GPIO_H_
-#define _TEGRA_GPIO_H_
+#ifndef _TEGRA20_GPIO_H_
+#define _TEGRA20_GPIO_H_
 
 /*
  * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
@@ -29,8 +29,8 @@
  */
 #define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
 #define TEGRA_GPIO_BANKS	7	/* number of banks */
-#define MAX_NUM_GPIOS		(TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
-#define GPIO_NAME_SIZE		20	/* gpio_request max label len */
+
+#include <asm/arch-tegra/gpio.h>
 
 /* GPIO Controller registers for a single bank */
 struct gpio_ctlr_bank {
@@ -48,11 +48,6 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-#define GPIO_BANK(x)		((x) >> 5)
-#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
-#define GPIO_FULLPORT(x)	((x) >> 3)
-#define GPIO_BIT(x)		((x) & 0x7)
-
 enum gpio_pin {
 	GPIO_PA0 = 0,	/* pin 0 */
 	GPIO_PA1,
@@ -280,11 +275,4 @@ enum gpio_pin {
 	GPIO_PBB7,	/* pin 223 */
 };
 
-/*
- * Tegra20-specific GPIO API
- */
-
-void gpio_info(void);
-
-#define gpio_status()	gpio_info()
-#endif	/* TEGRA_GPIO_H_ */
+#endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h
deleted file mode 100644
index 5c95047998..0000000000
--- a/arch/arm/include/asm/arch-tegra20/mmc.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2011, Google Inc. All rights reserved.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_MMC_H_
-#define _TEGRA_MMC_H_
-
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
-
-#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pmc.h b/arch/arm/include/asm/arch-tegra20/pmc.h
deleted file mode 100644
index b1d47cd2e3..0000000000
--- a/arch/arm/include/asm/arch-tegra20/pmc.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PMC_H_
-#define _PMC_H_
-
-/* Power Management Controller (APBDEV_PMC_) registers */
-struct pmc_ctlr {
-	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
-	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
-	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
-	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
-	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
-	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
-	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
-	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
-	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
-	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
-	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
-	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
-	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
-	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
-	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
-	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
-	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
-	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
-	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
-	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
-
-	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
-	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
-	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
-	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
-	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
-	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
-	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
-	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
-	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
-	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
-	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
-	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
-	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
-	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
-	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
-	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
-	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
-	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
-	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
-	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
-	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
-	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
-	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
-	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
-
-	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
-	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
-	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
-	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
-	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
-	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
-
-	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
-	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
-	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
-	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
-	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
-	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
-	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
-	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
-	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
-	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
-	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
-	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
-	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
-
-	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
-	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
-	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
-	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
-	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
-	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
-	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
-	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
-	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
-	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
-	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
-	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
-	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
-	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
-	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
-	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
-	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
-	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
-	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
-
-	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
-	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
-	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
-	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
-	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
-	uint pmc_gate;			/* _GATE_0, offset 15C */
-};
-
-#define CPU_PWRED	1
-#define CPU_CLMP	1
-
-#define PARTID_CP	0xFFFFFFF8
-#define START_CP	(1 << 8)
-
-#define CPUPWRREQ_OE	(1 << 16)
-
-#endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra20/scu.h b/arch/arm/include/asm/arch-tegra20/scu.h
deleted file mode 100644
index 787ded0fe0..0000000000
--- a/arch/arm/include/asm/arch-tegra20/scu.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SCU_H_
-#define _SCU_H_
-
-/* ARM Snoop Control Unit (SCU) registers */
-struct scu_ctlr {
-	uint scu_ctrl;		/* SCU Control Register, offset 00 */
-	uint scu_cfg;		/* SCU Config Register, offset 04 */
-	uint scu_cpu_pwr_stat;	/* SCU CPU Power Status Register, offset 08 */
-	uint scu_inv_all;	/* SCU Invalidate All Register, offset 0C */
-	uint scu_reserved0[12];	/* reserved, offset 10-3C */
-	uint scu_filt_start;	/* SCU Filtering Start Address Reg, offset 40 */
-	uint scu_filt_end;	/* SCU Filtering End Address Reg, offset 44 */
-	uint scu_reserved1[2];	/* reserved, offset 48-4C */
-	uint scu_acc_ctl;	/* SCU Access Control Register, offset 50 */
-	uint scu_ns_acc_ctl;	/* SCU Non-secure Access Cntrl Reg, offset 54 */
-};
-
-#define SCU_CTRL_ENABLE		(1 << 0)
-
-#endif	/* SCU_H */
diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 919aec7f74..ca98733262 100644
--- a/arch/arm/include/asm/arch-tegra20/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -21,15 +21,16 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
 
-struct tegra_sysinfo {
-	char *board_string;
-};
+#define NV_PA_SDRAM_BASE	0x00000000
 
-void invalidate_dcache(void);
+#include <asm/arch-tegra/tegra.h>
 
-extern const struct tegra_sysinfo sysinfo;
+#define TEGRA_USB1_BASE		0xC5000000
+#define TEGRA_USB3_BASE		0xC5008000
 
-#endif
+#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
+
+#endif	/* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h
deleted file mode 100644
index c9485a1c84..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra20.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_H_
-#define _TEGRA20_H_
-
-#define NV_PA_SDRAM_BASE	0x00000000
-#define NV_PA_ARM_PERIPHBASE	0x50040000
-#define NV_PA_PG_UP_BASE	0x60000000
-#define NV_PA_TMRUS_BASE	0x60005010
-#define NV_PA_CLK_RST_BASE	0x60006000
-#define NV_PA_FLOW_BASE		0x60007000
-#define NV_PA_GPIO_BASE		0x6000D000
-#define NV_PA_EVP_BASE		0x6000F000
-#define NV_PA_APB_MISC_BASE	0x70000000
-#define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
-#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
-#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
-#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
-#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
-#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
-#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
-#define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
-#define NV_PA_CSITE_BASE	0x70040000
-#define TEGRA_USB1_BASE		0xC5000000
-#define TEGRA_USB3_BASE		0xC5008000
-#define TEGRA_USB_ADDR_MASK	0xFFFFC000
-
-#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
-#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
-#define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
-#define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
-#define PG_UP_TAG_AVP		0xAAAAAAAA
-
-#ifndef __ASSEMBLY__
-struct timerus {
-	unsigned int cntr_1us;
-};
-
-/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define AP20_WB_RUN_ADDRESS	0x40020000
-
-#define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
-#define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
-#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
-
-/* These are the available SKUs (product types) for Tegra */
-enum {
-	SKU_ID_T20		= 0x8,
-	SKU_ID_T25SE		= 0x14,
-	SKU_ID_AP25		= 0x17,
-	SKU_ID_T25		= 0x18,
-	SKU_ID_AP25E		= 0x1b,
-	SKU_ID_T25E		= 0x1c,
-};
-
-/* These are the SOC categories that affect clocking */
-enum {
-	TEGRA_SOC_T20,
-	TEGRA_SOC_T25,
-
-	TEGRA_SOC_COUNT,
-	TEGRA_SOC_UNKNOWN	= -1,
-};
-
-#else  /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		NV_PA_PMC_BASE
-#endif
-
-#endif	/* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_i2c.h b/arch/arm/include/asm/arch-tegra20/tegra_i2c.h
deleted file mode 100644
index 6abfe4e80b..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra_i2c.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * NVIDIA Tegra20 I2C controller
- *
- * Copyright 2010-2011 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_I2C_H_
-#define _TEGRA_I2C_H_
-
-#include <asm/types.h>
-
-enum {
-	I2C_TIMEOUT_USEC = 10000,	/* Wait time for completion */
-	I2C_FIFO_DEPTH = 8,		/* I2C fifo depth */
-};
-
-enum i2c_transaction_flags {
-	I2C_IS_WRITE = 0x1,		/* for I2C write operation */
-	I2C_IS_10_BIT_ADDRESS = 0x2,	/* for 10-bit I2C slave address */
-	I2C_USE_REPEATED_START = 0x4,	/* for repeat start */
-	I2C_NO_ACK = 0x8,		/* for slave that won't generate ACK */
-	I2C_SOFTWARE_CONTROLLER	= 0x10,	/* for I2C transfer using GPIO */
-	I2C_NO_STOP = 0x20,
-};
-
-/* Contians the I2C transaction details */
-struct i2c_trans_info {
-	/* flags to indicate the transaction details */
-	enum i2c_transaction_flags flags;
-	u32 address;	/* I2C slave device address */
-	u32 num_bytes;	/* number of bytes to be transferred */
-	/*
-	 * Send/receive buffer. For the I2C send operation this buffer should
-	 * be filled with the data to be sent to the slave device. For the I2C
-	 * receive operation this buffer is filled with the data received from
-	 * the slave device.
-	 */
-	u8 *buf;
-	int is_10bit_address;
-};
-
-struct i2c_control {
-	u32 tx_fifo;
-	u32 rx_fifo;
-	u32 packet_status;
-	u32 fifo_control;
-	u32 fifo_status;
-	u32 int_mask;
-	u32 int_status;
-};
-
-struct dvc_ctlr {
-	u32 ctrl1;			/* 00: DVC_CTRL_REG1 */
-	u32 ctrl2;			/* 04: DVC_CTRL_REG2 */
-	u32 ctrl3;			/* 08: DVC_CTRL_REG3 */
-	u32 status;			/* 0C: DVC_STATUS_REG */
-	u32 ctrl;			/* 10: DVC_I2C_CTRL_REG */
-	u32 addr_data;			/* 14: DVC_I2C_ADDR_DATA_REG */
-	u32 reserved_0[2];		/* 18: */
-	u32 req;			/* 20: DVC_REQ_REGISTER */
-	u32 addr_data3;			/* 24: DVC_I2C_ADDR_DATA_REG_3 */
-	u32 reserved_1[6];		/* 28: */
-	u32 cnfg;			/* 40: DVC_I2C_CNFG */
-	u32 cmd_addr0;			/* 44: DVC_I2C_CMD_ADDR0 */
-	u32 cmd_addr1;			/* 48: DVC_I2C_CMD_ADDR1 */
-	u32 cmd_data1;			/* 4C: DVC_I2C_CMD_DATA1 */
-	u32 cmd_data2;			/* 50: DVC_I2C_CMD_DATA2 */
-	u32 reserved_2[2];		/* 54: */
-	u32 i2c_status;			/* 5C: DVC_I2C_STATUS */
-	struct i2c_control control;	/* 60 ~ 78 */
-};
-
-struct i2c_ctlr {
-	u32 cnfg;			/* 00: I2C_I2C_CNFG */
-	u32 cmd_addr0;			/* 04: I2C_I2C_CMD_ADDR0 */
-	u32 cmd_addr1;			/* 08: I2C_I2C_CMD_DATA1 */
-	u32 cmd_data1;			/* 0C: I2C_I2C_CMD_DATA2 */
-	u32 cmd_data2;			/* 10: DVC_I2C_CMD_DATA2 */
-	u32 reserved_0[2];		/* 14: */
-	u32 status;			/* 1C: I2C_I2C_STATUS */
-	u32 sl_cnfg;			/* 20: I2C_I2C_SL_CNFG */
-	u32 sl_rcvd;			/* 24: I2C_I2C_SL_RCVD */
-	u32 sl_status;			/* 28: I2C_I2C_SL_STATUS */
-	u32 sl_addr1;			/* 2C: I2C_I2C_SL_ADDR1 */
-	u32 sl_addr2;			/* 30: I2C_I2C_SL_ADDR2 */
-	u32 reserved_1[2];		/* 34: */
-	u32 sl_delay_count;		/* 3C: I2C_I2C_SL_DELAY_COUNT */
-	u32 reserved_2[4];		/* 40: */
-	struct i2c_control control;	/* 50 ~ 68 */
-};
-
-/* bit fields definitions for IO Packet Header 1 format */
-#define PKT_HDR1_PROTOCOL_SHIFT		4
-#define PKT_HDR1_PROTOCOL_MASK		(0xf << PKT_HDR1_PROTOCOL_SHIFT)
-#define PKT_HDR1_CTLR_ID_SHIFT		12
-#define PKT_HDR1_CTLR_ID_MASK		(0xf << PKT_HDR1_CTLR_ID_SHIFT)
-#define PKT_HDR1_PKT_ID_SHIFT		16
-#define PKT_HDR1_PKT_ID_MASK		(0xff << PKT_HDR1_PKT_ID_SHIFT)
-#define PROTOCOL_TYPE_I2C		1
-
-/* bit fields definitions for IO Packet Header 2 format */
-#define PKT_HDR2_PAYLOAD_SIZE_SHIFT	0
-#define PKT_HDR2_PAYLOAD_SIZE_MASK	(0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
-
-/* bit fields definitions for IO Packet Header 3 format */
-#define PKT_HDR3_READ_MODE_SHIFT	19
-#define PKT_HDR3_READ_MODE_MASK		(1 << PKT_HDR3_READ_MODE_SHIFT)
-#define PKT_HDR3_SLAVE_ADDR_SHIFT	0
-#define PKT_HDR3_SLAVE_ADDR_MASK	(0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
-
-#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT	26
-#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK	\
-				(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
-
-/* I2C_CNFG */
-#define I2C_CNFG_NEW_MASTER_FSM_SHIFT	11
-#define I2C_CNFG_NEW_MASTER_FSM_MASK	(1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
-#define I2C_CNFG_PACKET_MODE_SHIFT	10
-#define I2C_CNFG_PACKET_MODE_MASK	(1 << I2C_CNFG_PACKET_MODE_SHIFT)
-
-/* I2C_SL_CNFG */
-#define I2C_SL_CNFG_NEWSL_SHIFT		2
-#define I2C_SL_CNFG_NEWSL_MASK		(1 << I2C_SL_CNFG_NEWSL_SHIFT)
-
-/* I2C_FIFO_STATUS */
-#define TX_FIFO_FULL_CNT_SHIFT		0
-#define TX_FIFO_FULL_CNT_MASK		(0xf << TX_FIFO_FULL_CNT_SHIFT)
-#define TX_FIFO_EMPTY_CNT_SHIFT		4
-#define TX_FIFO_EMPTY_CNT_MASK		(0xf << TX_FIFO_EMPTY_CNT_SHIFT)
-
-/* I2C_INTERRUPT_STATUS */
-#define I2C_INT_XFER_COMPLETE_SHIFT	7
-#define I2C_INT_XFER_COMPLETE_MASK	(1 << I2C_INT_XFER_COMPLETE_SHIFT)
-#define I2C_INT_NO_ACK_SHIFT		3
-#define I2C_INT_NO_ACK_MASK		(1 << I2C_INT_NO_ACK_SHIFT)
-#define I2C_INT_ARBITRATION_LOST_SHIFT	2
-#define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
-
-/**
- * Returns the bus number of the DVC controller
- *
- * @return number of bus, or -1 if there is no DVC active
- */
-int tegra_i2c_get_dvc_bus_num(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
deleted file mode 100644
index dd746cae0d..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __TEGRA_MMC_H_
-#define __TEGRA_MMC_H_
-
-#define TEGRA_SDMMC1_BASE	0xC8000000
-#define TEGRA_SDMMC2_BASE	0xC8000200
-#define TEGRA_SDMMC3_BASE	0xC8000400
-#define TEGRA_SDMMC4_BASE	0xC8000600
-
-#ifndef __ASSEMBLY__
-struct tegra_mmc {
-	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
-	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
-	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
-	unsigned int	argument;	/* _ARGUMENT_0 */
-	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
-	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
-	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
-	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
-	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
-	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
-	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
-	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
-	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
-	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
-	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
-	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
-	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
-	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
-	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
-	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
-	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
-	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
-	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
-	unsigned char	res1[2];	/* _RESERVED 31:16 */
-	unsigned int	capareg;	/* _CAPABILITIES_0 */
-	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
-	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
-	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
-	unsigned short	setacmd12err;	/* offset 50h */
-	unsigned short	setinterr;	/* offset 52h */
-	unsigned char	admaerr;	/* offset 54h */
-	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
-	unsigned long	admaaddr;	/* offset 58h-5Fh */
-	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
-	unsigned short	slotintstatus;	/* offset FCh */
-	unsigned short	hcver;		/* HOST Version */
-	unsigned char	res6[0x100];	/* RESERVED, offset 100h-1FFh */
-};
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
-
-struct mmc_host {
-	struct tegra_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
-	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
-	int pwr_gpio;		/* Power GPIO */
-	int cd_gpio;		/* Change Detect GPIO */
-};
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra_spi.h
deleted file mode 100644
index d53a93ff53..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * NVIDIA Tegra20 SPI-FLASH controller
- *
- * Copyright 2010-2012 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_SPI_H_
-#define _TEGRA_SPI_H_
-
-#include <asm/types.h>
-
-struct spi_tegra {
-	u32 command;	/* SPI_COMMAND_0 register  */
-	u32 status;	/* SPI_STATUS_0 register */
-	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
-	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
-	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
-	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
-	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
-};
-
-#define SPI_CMD_GO			(1 << 30)
-#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
-#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA			(1 << 21)
-#define SPI_CMD_ACTIVE_SDA_SHIFT	18
-#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL			(1 << 16)
-#define SPI_CMD_TXEN			(1 << 15)
-#define SPI_CMD_RXEN			(1 << 14)
-#define SPI_CMD_CS_VAL			(1 << 13)
-#define SPI_CMD_CS_SOFT			(1 << 12)
-#define SPI_CMD_CS_DELAY		(1 << 9)
-#define SPI_CMD_CS3_EN			(1 << 8)
-#define SPI_CMD_CS2_EN			(1 << 7)
-#define SPI_CMD_CS1_EN			(1 << 6)
-#define SPI_CMD_CS0_EN			(1 << 5)
-#define SPI_CMD_BIT_LENGTH		(1 << 4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
-
-#define SPI_STAT_BSY			(1 << 31)
-#define SPI_STAT_RDY			(1 << 30)
-#define SPI_STAT_RXF_FLUSH		(1 << 29)
-#define SPI_STAT_TXF_FLUSH		(1 << 28)
-#define SPI_STAT_RXF_UNR		(1 << 27)
-#define SPI_STAT_TXF_OVF		(1 << 26)
-#define SPI_STAT_RXF_EMPTY		(1 << 25)
-#define SPI_STAT_RXF_FULL		(1 << 24)
-#define SPI_STAT_TXF_EMPTY		(1 << 23)
-#define SPI_STAT_TXF_FULL		(1 << 22)
-#define SPI_STAT_SEL_TXRX_N		(1 << 16)
-#define SPI_STAT_CUR_BLKCNT		(1 << 15)
-
-#define SPI_TIMEOUT		1000
-#define TEGRA_SPI_MAX_FREQ	52000000
-
-#endif	/* _TEGRA_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h
deleted file mode 100644
index fdb99a73ee..0000000000
--- a/arch/arm/include/asm/arch-tegra20/timer.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Tegra20 timer functions */
-
-#ifndef _TEGRA_TIMER_H
-#define _TEGRA_TIMER_H
-
-/* returns the current monotonic timer value in microseconds */
-unsigned long timer_get_us(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/uart.h b/arch/arm/include/asm/arch-tegra20/uart.h
deleted file mode 100644
index aea29a7588..0000000000
--- a/arch/arm/include/asm/arch-tegra20/uart.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _UART_H_
-#define _UART_H_
-
-/* UART registers */
-struct uart_ctlr {
-	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
-	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
-	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
-	uint uart_lcr;			/* UART_LCR_0, offset 0C */
-	uint uart_mcr;			/* UART_MCR_0, offset 10 */
-	uint uart_lsr;			/* UART_LSR_0, offset 14 */
-	uint uart_msr;			/* UART_MSR_0, offset 18 */
-	uint uart_spr;			/* UART_SPR_0, offset 1C */
-	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
-	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
-	uint uart_asr;			/* UART_ASR_0, offset 3C */
-};
-
-#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
-#define NV_DEFAULT_DEBUG_BAUD		115200
-
-#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
-
-#endif	/* UART_H */
diff --git a/arch/arm/include/asm/arch-tegra20/warmboot.h b/arch/arm/include/asm/arch-tegra20/warmboot.h
deleted file mode 100644
index 99ac2e7d23..0000000000
--- a/arch/arm/include/asm/arch-tegra20/warmboot.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * (C) Copyright 2010, 2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _WARM_BOOT_H_
-#define _WARM_BOOT_H_
-
-#define STRAP_OPT_A_RAM_CODE_SHIFT	4
-#define STRAP_OPT_A_RAM_CODE_MASK	(0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
-
-/* Defines the supported operating modes */
-enum fuse_operating_mode {
-	MODE_PRODUCTION = 3,
-	MODE_UNDEFINED,
-};
-
-/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
-enum {
-	HASH_LENGTH = 4
-};
-
-/* Defines the storage for a hash value (128 bits) */
-struct hash {
-	u32 hash[HASH_LENGTH];
-};
-
-/*
- * Defines the code header information for the boot rom.
- *
- * The code immediately follows the code header.
- *
- * Note that the code header needs to be 16 bytes aligned to preserve
- * the alignment of relevant data for hash and decryption computations without
- * requiring extra copies to temporary memory areas.
- */
-struct wb_header {
-	u32 length_insecure;	/* length of the code header */
-	u32 reserved[3];
-	struct hash hash;	/* hash of header+code, starts next field*/
-	struct hash random_aes_block;	/* a data block to aid security. */
-	u32 length_secure;	/* length of the code header */
-	u32 destination;	/* destination address to put the wb code */
-	u32 entry_point;	/* execution address of the wb code */
-	u32 code_length;	/* length of the code */
-};
-
-/*
- * The warm boot code needs direct access to these registers since it runs in
- * SRAM and cannot call other U-Boot code.
- */
-union osc_ctrl_reg {
-	struct {
-		u32 xoe:1;
-		u32 xobp:1;
-		u32 reserved0:2;
-		u32 xofs:6;
-		u32 reserved1:2;
-		u32 xods:5;
-		u32 reserved2:3;
-		u32 oscfi_spare:8;
-		u32 pll_ref_div:2;
-		u32 osc_freq:2;
-	};
-	u32 word;
-};
-
-union pllx_base_reg {
-	struct {
-		u32 divm:5;
-		u32 reserved0:3;
-		u32 divn:10;
-		u32 reserved1:2;
-		u32 divp:3;
-		u32 reserved2:4;
-		u32 lock:1;
-		u32 reserved3:1;
-		u32 ref_dis:1;
-		u32 enable:1;
-		u32 bypass:1;
-	};
-	u32 word;
-};
-
-union pllx_misc_reg {
-	struct {
-		u32 vcocon:4;
-		u32 lfcon:4;
-		u32 cpcon:4;
-		u32 lock_sel:6;
-		u32 reserved0:1;
-		u32 lock_enable:1;
-		u32 reserved1:1;
-		u32 dccon:1;
-		u32 pts:2;
-		u32 reserved2:6;
-		u32 out1_div_byp:1;
-		u32 out1_inv_clk:1;
-	};
-	u32 word;
-};
-
-/*
- * TODO: This register is not documented in the TRM yet. We could move this
- * into the EMC and give it a proper interface, but not while it is
- * undocumented.
- */
-union scratch3_reg {
-	struct {
-		u32 pllx_base_divm:5;
-		u32 pllx_base_divn:10;
-		u32 pllx_base_divp:3;
-		u32 pllx_misc_lfcon:4;
-		u32 pllx_misc_cpcon:4;
-	};
-	u32 word;
-};
-
-
-/**
- * Save warmboot memory settings for a later resume
- *
- * @return 0 if ok, -1 on error
- */
-int warmboot_save_sdram_params(void);
-
-int warmboot_prepare_code(u32 seg_address, u32 seg_length);
-int sign_data_block(u8 *source, u32 length, u8 *signature);
-void wb_start(void);	/* Start of WB assembly code */
-void wb_end(void);	/* End of WB assembly code */
-
-#endif