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| author | Tom Rini <trini@konsulko.com> | 2021-04-16 08:30:25 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-04-16 08:30:25 -0400 |
| commit | 7cb977fd51b4ddcfe385749f035cc768a968edfb (patch) | |
| tree | 33c8354d42d619b8312e75d88a087eef254e1619 /arch/arm/include/asm | |
| parent | a6232e065dd9e349bf5908c928734c6b5b018112 (diff) | |
| parent | 599177ed5139dbab112d0c9603e18382d0c642ba (diff) | |
| download | u-boot-WIP/16Apr2021.tar.gz | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/16Apr2021
This adds support for devices with R40 dual rank DRAM, and asymmetric
A64 DRAM devices like the Pinephone/3GB.
Also we enable automatic gzipped kernel support, and allow scripted
DT overlay support. The rest of the patches are cleanups, but also
some sunxi-specific preparatory patches for USB3.0 and improved HDMI
support. The bulk of those changes will go through other trees, though.
Build-tested for all 156 sunxi boards, and boot tested on a A64, A20, R40,
H5, H6 and H616 board. USB, SD card, eMMC, HDMI and Ethernet all work
there (where applicable), with the exception of Ethernet on the H5. Since
this is already broken in v2021.04, I will send a separate fix.
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index a5a7ebde44..e843c14202 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg { #define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) /* The eight data lines (DQn) plus DM, DQS and DQSN */ #define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para { + +struct rank_para { u16 page_size; - u8 bus_full_width; - u8 dual_rank; u8 row_bits; u8 bank_bits; +}; + +struct dram_para { + u8 dual_rank; + u8 bus_full_width; + struct rank_para ranks[2]; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 ac_delays[31]; |