Merge branch '2021-04-11-remove-non-migrated-boards'WIP/11Apr2021

- Remove a large number of boards that have not migrated to DM_MMC, for
  which the migration deadline with 2 years ago at v2019.04.

9 files changed, 0 insertions, 1307 deletions

diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h
deleted file mode 100644
index 70846094e8..0000000000
--- a/arch/arm/include/asm/arch-s32v234/clock.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_BUS_CLK,
-	MXC_PERIPHERALS_CLK,
-	MXC_UART_CLK,
-	MXC_USDHC_CLK,
-	MXC_FEC_CLK,
-	MXC_I2C_CLK,
-};
-enum pll_type {
-	ARM_PLL = 0,
-	PERIPH_PLL,
-	ENET_PLL,
-	DDR_PLL,
-	VIDEO_PLL,
-};
-
-unsigned int mxc_get_clock(enum mxc_clock clk);
-void clock_init(void);
-
-#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h
deleted file mode 100644
index 8c709af80d..0000000000
--- a/arch/arm/include/asm/arch-s32v234/ddr.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
-#define __ARCH_ARM_MACH_S32V234_DDR_H__
-
-#define DDR0	0
-#define DDR1	1
-
-/* DDR offset in MSCR register */
-#define _DDR0_RESET	168
-#define _DDR0_CLK0	169
-#define _DDR0_CAS	170
-#define _DDR0_RAS	171
-#define _DDR0_WE_B	172
-#define _DDR0_CKE0	173
-#define _DDR0_CKE1	174
-#define _DDR0_CS_B0	175
-#define _DDR0_CS_B1	176
-#define _DDR0_BA0	177
-#define _DDR0_BA1	178
-#define _DDR0_BA2	179
-#define _DDR0_A0	180
-#define _DDR0_A1	181
-#define _DDR0_A2	182
-#define _DDR0_A3	183
-#define _DDR0_A4	184
-#define _DDR0_A5	185
-#define _DDR0_A6	186
-#define _DDR0_A7	187
-#define _DDR0_A8	188
-#define _DDR0_A9	189
-#define _DDR0_A10	190
-#define _DDR0_A11	191
-#define _DDR0_A12	192
-#define _DDR0_A13	193
-#define _DDR0_A14	194
-#define _DDR0_A15	195
-#define _DDR0_DM0	196
-#define _DDR0_DM1	197
-#define _DDR0_DM2	198
-#define _DDR0_DM3	199
-#define _DDR0_DQS0	200
-#define _DDR0_DQS1	201
-#define _DDR0_DQS2	202
-#define _DDR0_DQS3	203
-#define _DDR0_D0	204
-#define _DDR0_D1	205
-#define _DDR0_D2	206
-#define _DDR0_D3	207
-#define _DDR0_D4	208
-#define _DDR0_D5	209
-#define _DDR0_D6	210
-#define _DDR0_D7	211
-#define _DDR0_D8	212
-#define _DDR0_D9	213
-#define _DDR0_D10	214
-#define _DDR0_D11	215
-#define _DDR0_D12	216
-#define _DDR0_D13	217
-#define _DDR0_D14	218
-#define _DDR0_D15	219
-#define _DDR0_D16	220
-#define _DDR0_D17	221
-#define _DDR0_D18	222
-#define _DDR0_D19	223
-#define _DDR0_D20	224
-#define _DDR0_D21	225
-#define _DDR0_D22	226
-#define _DDR0_D23	227
-#define _DDR0_D24	228
-#define _DDR0_D25	229
-#define _DDR0_D26	230
-#define _DDR0_D27	231
-#define _DDR0_D28	232
-#define _DDR0_D29	233
-#define _DDR0_D30	234
-#define _DDR0_D31	235
-#define _DDR0_ODT0	236
-#define _DDR0_ODT1	237
-#define _DDR0_ZQ	238
-#define _DDR1_RESET	239
-#define _DDR1_CLK0	240
-#define _DDR1_CAS	241
-#define _DDR1_RAS	242
-#define _DDR1_WE_B	243
-#define _DDR1_CKE0	244
-#define _DDR1_CKE1	245
-#define _DDR1_CS_B0	246
-#define _DDR1_CS_B1	247
-#define _DDR1_BA0	248
-#define _DDR1_BA1	249
-#define _DDR1_BA2	250
-#define _DDR1_A0	251
-#define _DDR1_A1	252
-#define _DDR1_A2	253
-#define _DDR1_A3	254
-#define _DDR1_A4	255
-#define _DDR1_A5	256
-#define _DDR1_A6	257
-#define _DDR1_A7	258
-#define _DDR1_A8	259
-#define _DDR1_A9	260
-#define _DDR1_A10	261
-#define _DDR1_A11	262
-#define _DDR1_A12	263
-#define _DDR1_A13	264
-#define _DDR1_A14	265
-#define _DDR1_A15	266
-#define _DDR1_DM0	267
-#define _DDR1_DM1	268
-#define _DDR1_DM2	269
-#define _DDR1_DM3	270
-#define _DDR1_DQS0	271
-#define _DDR1_DQS1	272
-#define _DDR1_DQS2	273
-#define _DDR1_DQS3	274
-#define _DDR1_D0	275
-#define _DDR1_D1	276
-#define _DDR1_D2	277
-#define _DDR1_D3	278
-#define _DDR1_D4	279
-#define _DDR1_D5	280
-#define _DDR1_D6	281
-#define _DDR1_D7	282
-#define _DDR1_D8	283
-#define _DDR1_D9	284
-#define _DDR1_D10	285
-#define _DDR1_D11	286
-#define _DDR1_D12	287
-#define _DDR1_D13	288
-#define _DDR1_D14	289
-#define _DDR1_D15	290
-#define _DDR1_D16	291
-#define _DDR1_D17	292
-#define _DDR1_D18	293
-#define _DDR1_D19	294
-#define _DDR1_D20	295
-#define _DDR1_D21	296
-#define _DDR1_D22	297
-#define _DDR1_D23	298
-#define _DDR1_D24	299
-#define _DDR1_D25	300
-#define _DDR1_D26	301
-#define _DDR1_D27	302
-#define _DDR1_D28	303
-#define _DDR1_D29	304
-#define _DDR1_D30	305
-#define _DDR1_D31	306
-#define _DDR1_ODT0	307
-#define _DDR1_ODT1	308
-#define _DDR1_ZQ	309
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h
deleted file mode 100644
index 1472a43f1b..0000000000
--- a/arch/arm/include/asm/arch-s32v234/imx-regs.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_IMX_REGS_H__
-#define __ASM_ARCH_IMX_REGS_H__
-
-#define ARCH_MXC
-
-#define IRAM_BASE_ADDR      0x3E800000	/* internal ram */
-#define IRAM_SIZE           0x00400000	/* 4MB */
-
-#define AIPS0_BASE_ADDR     (0x40000000UL)
-#define AIPS1_BASE_ADDR     (0x40080000UL)
-
-/* AIPS 0 */
-#define AXBS_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00000000)
-#define CSE3_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00001000)
-#define EDMA_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00002000)
-#define XRDC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00004000)
-#define SWT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000A000)
-#define SWT1_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000B000)
-#define STM0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000D000)
-#define NIC301_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00010000)
-#define GC3000_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00020000)
-#define DEC200_DECODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00026000)
-#define DEC200_ENCODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00027000)
-#define TWOD_ACE_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00028000)
-#define MIPI_CSI0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00030000)
-#define DMAMUX0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00031000)
-#define ENET_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00032000)
-#define FLEXRAY_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00034000)
-#define MMDC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00036000)
-#define MEW0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00037000)
-#define MONITOR_DDR0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00038000)
-#define MONITOR_CCI0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00039000)
-#define PIT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0003A000)
-#define MC_CGM0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003C000)
-#define MC_CGM1_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003F000)
-#define MC_CGM2_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00042000)
-#define MC_CGM3_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00045000)
-#define MC_RGM_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00048000)
-#define MC_ME_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004A000)
-#define MC_PCU_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004B000)
-#define ADC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004D000)
-#define FLEXTIMER_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004F000)
-#define I2C0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00051000)
-#define LINFLEXD0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00053000)
-#define FLEXCAN0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00055000)
-#define SPI0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00057000)
-#define SPI2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00059000)
-#define CRC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005B000)
-#define USDHC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005D000)
-#define OCOTP_CONTROLLER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0005F000)
-#define WKPU_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00063000)
-#define VIU0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00064000)
-#define HPSMI_SRAM_CONTROLLER_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00068000)
-#define SIUL2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0006C000)
-#define SIPI_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00074000)
-#define LFAST_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00078000)
-#define SSE_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00079000)
-#define SRC_SOC_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0007C000)
-
-/* AIPS 1 */
-#define ERM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000000000)
-#define MSCM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000001000)
-#define SEMA42_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000002000)
-#define INTC_MON_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000003000)
-#define SWT2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000004000)
-#define SWT3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000005000)
-#define SWT4_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000006000)
-#define STM1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000007000)
-#define EIM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000008000)
-#define APB_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000009000)
-#define XBIC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000012000)
-#define MIPI_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000020000)
-#define DMAMUX1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000021000)
-#define MMDC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000022000)
-#define MEW1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000023000)
-#define DDR1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000024000)
-#define CCI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000025000)
-#define QUADSPI0_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000026000)
-#define PIT1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00002A000)
-#define FCCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000030000)
-#define FLEXTIMER_FTM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0X000036000)
-#define I2C1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000038000)
-#define I2C2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00003A000)
-#define LINFLEXD1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003C000)
-#define FLEXCAN1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003E000)
-#define SPI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000040000)
-#define SPI3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000042000)
-#define IPL_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000043000)
-#define CGM_CMU_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000044000)
-#define PMC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000048000)
-#define CRC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004C000)
-#define TMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004E000)
-#define VIU1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000050000)
-#define JPEG_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000054000)
-#define H264_DEC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000058000)
-#define H264_ENC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00005C000)
-#define MEMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000060000)
-#define STCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000064000)
-#define SLFTST_CTRL_BASE_ADDR			(AIPS1_BASE_ADDR + 0X000066000)
-#define MCT_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000068000)
-#define REP_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00006A000)
-#define MBIST_CONTROLLER_BASE_ADDR		(AIPS1_BASE_ADDR + 0X00006C000)
-#define BOOT_LOADER_BASE_ADDR			(AIPS1_BASE_ADDR + 0X00006F000)
-
-/* TODO Remove this after the IOMUX framework is implemented */
-#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
-
-/* MUX mode and PAD ctrl are in one register */
-#define CONFIG_IOMUX_SHARE_CONF_REG
-
-#define FEC_QUIRK_ENET_MAC
-#define I2C_QUIRK_REG
-
-/* MSCM interrupt router */
-#define MSCM_IRSPRC_CPn_EN		3
-#define MSCM_IRSPRC_NUM			176
-#define MSCM_CPXTYPE_RYPZ_MASK		0xFF
-#define MSCM_CPXTYPE_RYPZ_OFFSET	0
-#define MSCM_CPXTYPE_PERS_MASK		0xFFFFFF00
-#define MSCM_CPXTYPE_PERS_OFFSET	8
-#define MSCM_CPXTYPE_PERS_A53		0x413533
-#define MSCM_CPXTYPE_PERS_CM4		0x434d34
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* System Reset Controller (SRC) */
-struct src {
-	u32 bmr1;
-	u32 bmr2;
-	u32 gpr1_boot;
-	u32 reserved_0x00C[61];
-	u32 gpr1;
-	u32 gpr2;
-	u32 gpr3;
-	u32 gpr4;
-	u32 gpr5;
-	u32 gpr6;
-	u32 gpr7;
-	u32 reserved_0x11C[1];
-	u32 gpr9;
-	u32 gpr10;
-	u32 gpr11;
-	u32 gpr12;
-	u32 gpr13;
-	u32 gpr14;
-	u32 gpr15;
-	u32 gpr16;
-	u32 reserved_0x140[1];
-	u32 gpr17;
-	u32 gpr18;
-	u32 gpr19;
-	u32 gpr20;
-	u32 gpr21;
-	u32 gpr22;
-	u32 gpr23;
-	u32 gpr24;
-	u32 gpr25;
-	u32 gpr26;
-	u32 gpr27;
-	u32 reserved_0x16C[5];
-	u32 pcie_config1;
-	u32 ddr_self_ref_ctrl;
-	u32 pcie_config0;
-	u32 reserved_0x18C[4];
-	u32 soc_misc_config2;
-};
-
-/* SRC registers definitions */
-
-/* SRC_GPR1 */
-#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
-										(SRC_GPR1_PLL_OFFSET + (pll)) )
-#define SRC_GPR1_PLL_SOURCE_MASK	(0x1)
-
-#define SRC_GPR1_PLL_OFFSET			(27)
-#define SRC_GPR1_FIRC_CLK_SOURCE	(0x0)
-#define SRC_GPR1_XOSC_CLK_SOURCE	(0x1)
-
-/* Periodic Interrupt Timer (PIT) */
-struct pit_reg {
-	u32 mcr;
-	u32 recv0[55];
-	u32 ltmr64h;
-	u32 ltmr64l;
-	u32 recv1[6];
-	u32 ldval0;
-	u32 cval0;
-	u32 tctrl0;
-	u32 tflg0;
-	u32 ldval1;
-	u32 cval1;
-	u32 tctrl1;
-	u32 tflg1;
-	u32 ldval2;
-	u32 cval2;
-	u32 tctrl2;
-	u32 tflg2;
-	u32 ldval3;
-	u32 cval3;
-	u32 tctrl3;
-	u32 tflg3;
-	u32 ldval4;
-	u32 cval4;
-	u32 tctrl4;
-	u32 tflg4;
-	u32 ldval5;
-	u32 cval5;
-	u32 tctrl5;
-	u32 tflg5;
-};
-
-/* Watchdog Timer (WDOG) */
-struct wdog_regs {
-	u32 cr;
-	u32 ir;
-	u32 to;
-	u32 wn;
-	u32 sr;
-	u32 co;
-	u32 sk;
-};
-
-/* UART */
-struct linflex_fsl {
-	u32 lincr1;
-	u32 linier;
-	u32 linsr;
-	u32 linesr;
-	u32 uartcr;
-	u32 uartsr;
-	u32 lintcsr;
-	u32 linocr;
-	u32 lintocr;
-	u32 linfbrr;
-	u32 linibrr;
-	u32 lincfr;
-	u32 lincr2;
-	u32 bidr;
-	u32 bdrl;
-	u32 bdrm;
-	u32 ifer;
-	u32 ifmi;
-	u32 ifmr;
-	u32 ifcr0;
-	u32 ifcr1;
-	u32 ifcr2;
-	u32 ifcr3;
-	u32 ifcr4;
-	u32 ifcr5;
-	u32 ifcr6;
-	u32 ifcr7;
-	u32 ifcr8;
-	u32 ifcr9;
-	u32 ifcr10;
-	u32 ifcr11;
-	u32 ifcr12;
-	u32 ifcr13;
-	u32 ifcr14;
-	u32 ifcr15;
-	u32 gcr;
-	u32 uartpto;
-	u32 uartcto;
-	u32 dmatxe;
-	u32 dmarxe;
-};
-
-/* MSCM Interrupt Router */
-struct mscm_ir {
-	u32 cpxtype;		/* Processor x Type Register                    */
-	u32 cpxnum;		/* Processor x Number Register                  */
-	u32 cpxmaster;		/* Processor x Master Number Register   */
-	u32 cpxcount;		/* Processor x Count Register                   */
-	u32 cpxcfg0;		/* Processor x Configuration 0 Register */
-	u32 cpxcfg1;		/* Processor x Configuration 1 Register */
-	u32 cpxcfg2;		/* Processor x Configuration 2 Register */
-	u32 cpxcfg3;		/* Processor x Configuration 3 Register */
-	u32 cp0type;		/* Processor 0 Type Register                    */
-	u32 cp0num;		/* Processor 0 Number Register                  */
-	u32 cp0master;		/* Processor 0 Master Number Register   */
-	u32 cp0count;		/* Processor 0 Count Register                   */
-	u32 cp0cfg0;		/* Processor 0 Configuration 0 Register */
-	u32 cp0cfg1;		/* Processor 0 Configuration 1 Register */
-	u32 cp0cfg2;		/* Processor 0 Configuration 2 Register */
-	u32 cp0cfg3;		/* Processor 0 Configuration 3 Register */
-	u32 cp1type;		/* Processor 1 Type Register                    */
-	u32 cp1num;		/* Processor 1 Number Register                  */
-	u32 cp1master;		/* Processor 1 Master Number Register   */
-	u32 cp1count;		/* Processor 1 Count Register                   */
-	u32 cp1cfg0;		/* Processor 1 Configuration 0 Register */
-	u32 cp1cfg1;		/* Processor 1 Configuration 1 Register */
-	u32 cp1cfg2;		/* Processor 1 Configuration 2 Register */
-	u32 cp1cfg3;		/* Processor 1 Configuration 3 Register */
-	u32 reserved_0x060[232];
-	u32 ocmdr0;		/* On-Chip Memory Descriptor Register   */
-	u32 reserved_0x404[2];
-	u32 ocmdr3;		/* On-Chip Memory Descriptor Register   */
-	u32 reserved_0x410[28];
-	u32 tcmdr[4];		/* Generic Tightly Coupled Memory Descriptor Register   */
-	u32 reserved_0x490[28];
-	u32 cpce0;		/* Core Parity Checking Enable Register 0                               */
-	u32 reserved_0x504[191];
-	u32 ircp0ir;		/* Interrupt Router CP0 Interrupt Register                              */
-	u32 ircp1ir;		/* Interrupt Router CP1 Interrupt Register                              */
-	u32 reserved_0x808[6];
-	u32 ircpgir;		/* Interrupt Router CPU Generate Interrupt Register             */
-	u32 reserved_0x824[23];
-	u16 irsprc[176];	/* Interrupt Router Shared Peripheral Routing Control Register  */
-	u32 reserved_0x9e0[136];
-	u32 iahbbe0;		/* Gasket Burst Enable Register                                                 */
-	u32 reserved_0xc04[63];
-	u32 ipcge;		/* Interconnect Parity Checking Global Enable Register  */
-	u32 reserved_0xd04[3];
-	u32 ipce[4];		/* Interconnect Parity Checking Enable Register                 */
-	u32 reserved_0xd20[8];
-	u32 ipcgie;		/* Interconnect Parity Checking Global Injection Enable Register        */
-	u32 reserved_0xd44[3];
-	u32 ipcie[4];		/* Interconnect Parity Checking Injection Enable Register       */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h
deleted file mode 100644
index c5efee5b75..0000000000
--- a/arch/arm/include/asm/arch-s32v234/lpddr2.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
-#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
-
-/* definitions for LPDDR2 PAD values */
-#define LPDDR2_CLK0_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
-	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 |			\
-	 SIUL2_MSCR_DCYCLE_TRIM_NONE)
-#define LPDDR2_CKEn_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
-	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_CS_Bn_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
-	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_DMn_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
-	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_DQSn_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
-	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN |						\
-	 SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
-#define LPDDR2_An_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
-	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
-	 SIUL2_MSCR_PUS_100K_UP)
-#define LPDDR2_Dn_PAD	\
-	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
-	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
-	 SIUL2_MSCR_PUS_100K_UP)
-
-#define _MDCTL							0x03010000
-
-#define MMDC_MDSCR_CFG_VALUE			0x00008000	/* Set MDSCR[CON_REQ] (configuration request) */
-#define MMDC_MDCFG0_VALUE				0x464F61A5	/* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
-#define MMDC_MDCFG1_VALUE				0x00180E63	/* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
-#define MMDC_MDCFG2_VALUE				0x000000DD	/* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
-#define MMDC_MDCFG3LP_VALUE				0x001F099B	/* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
-#define MMDC_MDOTC_VALUE				0x00000000	/* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
-#define MMDC_MDMISC_VALUE				0x00001688	/* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
-#define MMDC_MDOR_VALUE					0x00000010	/* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
-#define MMDC_MPMUR0_VALUE				0x00000800	/* Force delay line initialisation */
-#define MMDC_MDSCR_RST_VALUE			0x003F8030	/* Reset command CS0 */
-#define MMDC_MPZQLP2CTL_VALUE			0x1B5F0109	/* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
-#define MMDC_MPZQHWCTRL_VALUE			0xA0010003	/* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
-#define MMDC_MDSCR_MR1_VALUE			0xC2018030	/* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
-#define MMDC_MDSCR_MR2_VALUE			0x06028030	/* Configure MR2: RL=8, WL=4 */
-#define MMDC_MDSCR_MR3_VALUE			0x01038030	/* Configure MR3: DS=34R */
-#define MMDC_MDSCR_MR10_VALUE			0xFF0A8030	/* Configure MR10: Calibration at init */
-#define MMDC_MDASP_MODULE0_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0x90000000) */
-#define MMDC_MPRDDLCTL_MODULE0_VALUE	0x4D4B4F4B	/* Read delay line offsets */
-#define MMDC_MPWRDLCTL_MODULE0_VALUE	0x38383737	/* Write delay line offsets */
-#define MMDC_MPDGCTRL0_MODULE0_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
-#define MMDC_MPDGCTRL1_MODULE0_VALUE	0x00000000	/* Read DQS gating control 1 */
-#define MMDC_MDASP_MODULE1_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0xD0000000) */
-#define MMDC_MPRDDLCTL_MODULE1_VALUE	0x4D4B4F4B	/* Read delay line offsets */
-#define MMDC_MPWRDLCTL_MODULE1_VALUE	0x38383737	/* Write delay line offsets */
-#define MMDC_MPDGCTRL0_MODULE1_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
-#define MMDC_MPDGCTRL1_MODULE1_VALUE	0x00000000	/* Read DQS gating control 1 */
-#define MMDC_MDRWD_VALUE				0x0F9F26D2	/* Read/write command delay - default used */
-#define MMDC_MDPDC_VALUE				0x00020024	/* Power down control */
-#define MMDC_MDREF_VALUE				0x30B01800	/* Refresh control */
-#define MMDC_MPODTCTRL_VALUE			0x00000000	/* No ODT */
-#define MMDC_MDSCR_DEASSERT_VALUE				0x00000000	/* Deassert the configuration request */
-
-/* set I/O pads for DDR */
-void lpddr2_config_iomux(uint8_t module);
-void config_mmdc(uint8_t module);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
deleted file mode 100644
index 957d48f9c0..0000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
-
-#ifndef __ASSEMBLY__
-
-/* MC_CGM registers definitions */
-/* MC_CGM_SC_SS */
-#define CGM_SC_SS(cgm_addr)			( ((cgm_addr) + 0x000007E4) )
-#define MC_CGM_SC_SEL_FIRC			(0x0)
-#define MC_CGM_SC_SEL_XOSC			(0x1)
-#define MC_CGM_SC_SEL_ARMPLL		(0x2)
-#define MC_CGM_SC_SEL_CLKDISABLE	(0xF)
-
-/* MC_CGM_SC_DCn */
-#define CGM_SC_DCn(cgm_addr,dc)		( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
-#define MC_CGM_SC_DCn_PREDIV(val)	(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
-#define MC_CGM_SC_DCn_PREDIV_MASK	(0x00070000)
-#define MC_CGM_SC_DCn_PREDIV_OFFSET	(16)
-#define MC_CGM_SC_DCn_DE			(1 << 31)
-#define MC_CGM_SC_SEL_MASK			(0x0F000000)
-#define MC_CGM_SC_SEL_OFFSET		(24)
-
-/* MC_CGM_ACn_DCm */
-#define CGM_ACn_DCm(cgm_addr,ac,dc)		( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
-#define MC_CGM_ACn_DCm_PREDIV(val)		(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
-
-/*
- * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
- * that the 5th bit is always ignored during writes if the current
- * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
- *
- * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
- *
- * This should be changed if any problems occur.
- */
-#define MC_CGM_ACn_DCm_PREDIV_MASK		(0x001F0000)
-#define MC_CGM_ACn_DCm_PREDIV_OFFSET	(16)
-#define MC_CGM_ACn_DCm_DE				(1 << 31)
-
-/*
- * MC_CGM_ACn_SC/MC_CGM_ACn_SS
- */
-#define CGM_ACn_SC(cgm_addr,ac)			((cgm_addr + 0x00000800) + ((ac) * 0x20))
-#define CGM_ACn_SS(cgm_addr,ac)			((cgm_addr + 0x00000804) + ((ac) * 0x20))
-#define MC_CGM_ACn_SEL_MASK				(0x07000000)
-#define MC_CGM_ACn_SEL_SET(source)		(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
-#define MC_CGM_ACn_SEL_OFFSET			(24)
-
-#define MC_CGM_ACn_SEL_FIRC				(0x0)
-#define MC_CGM_ACn_SEL_XOSC				(0x1)
-#define MC_CGM_ACn_SEL_ARMPLL			(0x2)
-/*
- * According to the manual some PLL can be divided by X (X={1,3,5}):
- * PERPLLDIVX, VIDEOPLLDIVX.
- */
-#define MC_CGM_ACn_SEL_PERPLLDIVX		(0x3)
-#define MC_CGM_ACn_SEL_ENETPLL			(0x4)
-#define MC_CGM_ACn_SEL_DDRPLL			(0x5)
-#define MC_CGM_ACn_SEL_EXTSRCPAD		(0x7)
-#define MC_CGM_ACn_SEL_SYSCLK			(0x8)
-#define MC_CGM_ACn_SEL_VIDEOPLLDIVX		(0x9)
-#define MC_CGM_ACn_SEL_PERCLK			(0xA)
-
-/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
-#define PLLDIG_PLLDV(pll)				((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
-#define PLLDIG_PLLDV_MFD(div)			(PLLDIG_PLLDV_MFD_MASK & (div))
-#define PLLDIG_PLLDV_MFD_MASK			(0x000000FF)
-
-/*
- * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
- * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
- */
-#define PLLDIG_PLLDV_RFDPHI_SET(val)	(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
-#define PLLDIG_PLLDV_RFDPHI_MASK		(0x003F0000)
-#define PLLDIG_PLLDV_RFDPHI_MAXVALUE	(0x3F)
-#define PLLDIG_PLLDV_RFDPHI_OFFSET		(16)
-
-#define PLLDIG_PLLDV_RFDPHI1_SET(val)	(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
-#define PLLDIG_PLLDV_RFDPHI1_MASK		(0x7E000000)
-#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE	(0x3F)
-#define PLLDIG_PLLDV_RFDPHI1_OFFSET		(25)
-
-#define PLLDIG_PLLDV_PREDIV_SET(val)	(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
-#define PLLDIG_PLLDV_PREDIV_MASK		(0x00007000)
-#define PLLDIG_PLLDV_PREDIV_MAXVALUE	(0x7)
-#define PLLDIG_PLLDV_PREDIV_OFFSET		(12)
-
-/* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
-#define PLLDIG_PLLFD(pll)				((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
-#define PLLDIG_PLLFD_MFN_SET(val)		(PLLDIG_PLLFD_MFN_MASK & (val))
-#define PLLDIG_PLLFD_MFN_MASK			(0x00007FFF)
-#define PLLDIG_PLLFD_SMDEN				(1 << 30)
-
-/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
-#define PLLDIG_PLLCAL1(pll)				((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
-#define PLLDIG_PLLCAL1_NDAC1_SET(val)	(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
-#define PLLDIG_PLLCAL1_NDAC1_OFFSET		(24)
-#define PLLDIG_PLLCAL1_NDAC1_MASK		(0x7F000000)
-
-/* Digital Frequency Synthesizer (DFS) */
-/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
-#define DFS0_BASE_ADDR				(MC_CGM0_BASE_ADDR + 0x00000040)
-
-/* DFS DLL Program Register 1 */
-#define DFS_DLLPRG1(pll)			(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
-
-#define DFS_DLLPRG1_V2IGC_SET(val)	(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
-#define DFS_DLLPRG1_V2IGC_OFFSET	(0)
-#define DFS_DLLPRG1_V2IGC_MASK		(0x00000007)
-
-#define DFS_DLLPRG1_LCKWT_SET(val)		(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
-#define DFS_DLLPRG1_LCKWT_OFFSET		(4)
-#define DFS_DLLPRG1_LCKWT_MASK			(0x00000030)
-
-#define DFS_DLLPRG1_DACIN_SET(val)		(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
-#define DFS_DLLPRG1_DACIN_OFFSET		(6)
-#define DFS_DLLPRG1_DACIN_MASK			(0x000001C0)
-
-#define DFS_DLLPRG1_CALBYPEN_SET(val)	(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
-#define DFS_DLLPRG1_CALBYPEN_OFFSET		(9)
-#define DFS_DLLPRG1_CALBYPEN_MASK		(0x00000200)
-
-#define DFS_DLLPRG1_VSETTLCTRL_SET(val)	(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
-#define DFS_DLLPRG1_VSETTLCTRL_OFFSET	(10)
-#define DFS_DLLPRG1_VSETTLCTRL_MASK		(0x00000C00)
-
-#define DFS_DLLPRG1_CPICTRL_SET(val)	(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
-#define DFS_DLLPRG1_CPICTRL_OFFSET		(12)
-#define DFS_DLLPRG1_CPICTRL_MASK		(0x00007000)
-
-/* DFS Control Register (DFS_CTRL) */
-#define DFS_CTRL(pll)					(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
-#define DFS_CTRL_DLL_LOLIE				(1 << 0)
-#define DFS_CTRL_DLL_RESET				(1 << 1)
-
-/* DFS Port Status Register (DFS_PORTSR) */
-#define DFS_PORTSR(pll)						(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
-/* DFS Port Reset Register (DFS_PORTRESET) */
-#define DFS_PORTRESET(pll)					(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
-#define DFS_PORTRESET_PORTRESET_SET(val)	(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
-#define DFS_PORTRESET_PORTRESET_MAXVAL		(0xF)
-#define DFS_PORTRESET_PORTRESET_MASK		(0x0000000F)
-#define DFS_PORTRESET_PORTRESET_OFFSET		(0)
-
-/* DFS Divide Register Portn (DFS_DVPORTn) */
-#define DFS_DVPORTn(pll,n)			(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
-
-/*
- * The mathematical formula for fdfs_clockout is the following:
- * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
- */
-#define DFS_DVPORTn_MFI_SET(val)	(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
-#define DFS_DVPORTn_MFN_SET(val)	(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
-#define DFS_DVPORTn_MFI_MASK		(0x0000FF00)
-#define DFS_DVPORTn_MFN_MASK		(0x000000FF)
-#define DFS_DVPORTn_MFI_MAXVAL		(0xFF)
-#define DFS_DVPORTn_MFN_MAXVAL		(0xFF)
-#define DFS_DVPORTn_MFI_OFFSET		(8)
-#define DFS_DVPORTn_MFN_OFFSET		(0)
-#define DFS_MAXNUMBER				(4)
-
-#define DFS_PARAMS_Nr				(3)
-
-/* Frequencies are in Hz */
-#define FIRC_CLK_FREQ				(48000000)
-#define XOSC_CLK_FREQ				(40000000)
-
-#define PLL_MIN_FREQ				(650000000)
-#define PLL_MAX_FREQ				(1300000000)
-
-#define ARM_PLL_PHI0_FREQ			(1000000000)
-#define ARM_PLL_PHI1_FREQ			(1000000000)
-/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
-#define ARM_PLL_PHI1_DFS1_EN		(1)
-#define ARM_PLL_PHI1_DFS1_MFI		(3)
-#define ARM_PLL_PHI1_DFS1_MFN		(194)
-/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
-#define ARM_PLL_PHI1_DFS2_EN		(1)
-#define ARM_PLL_PHI1_DFS2_MFI		(1)
-#define ARM_PLL_PHI1_DFS2_MFN		(170)
-/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
-#define ARM_PLL_PHI1_DFS3_EN		(1)
-#define ARM_PLL_PHI1_DFS3_MFI		(1)
-#define ARM_PLL_PHI1_DFS3_MFN		(170)
-#define ARM_PLL_PHI1_DFS_Nr			(3)
-#define ARM_PLL_PLLDV_PREDIV		(2)
-#define ARM_PLL_PLLDV_MFD			(50)
-#define ARM_PLL_PLLDV_MFN			(0)
-
-#define PERIPH_PLL_PHI0_FREQ		(400000000)
-#define PERIPH_PLL_PHI1_FREQ		(100000000)
-#define PERIPH_PLL_PHI1_DFS_Nr		(0)
-#define PERIPH_PLL_PLLDV_PREDIV		(1)
-#define PERIPH_PLL_PLLDV_MFD		(30)
-#define PERIPH_PLL_PLLDV_MFN		(0)
-
-#define ENET_PLL_PHI0_FREQ			(500000000)
-#define ENET_PLL_PHI1_FREQ			(1000000000)
-/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
-#define ENET_PLL_PHI1_DFS1_EN		(1)
-#define ENET_PLL_PHI1_DFS1_MFI		(2)
-#define ENET_PLL_PHI1_DFS1_MFN		(219)
-/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
-#define ENET_PLL_PHI1_DFS2_EN		(1)
-#define ENET_PLL_PHI1_DFS2_MFI		(2)
-#define ENET_PLL_PHI1_DFS2_MFN		(219)
-/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
-#define ENET_PLL_PHI1_DFS3_EN		(1)
-#define ENET_PLL_PHI1_DFS3_MFI		(3)
-#define ENET_PLL_PHI1_DFS3_MFN		(32)
-/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
-#define ENET_PLL_PHI1_DFS4_EN		(1)
-#define ENET_PLL_PHI1_DFS4_MFI		(2)
-#define ENET_PLL_PHI1_DFS4_MFN		(0)
-#define ENET_PLL_PHI1_DFS_Nr		(4)
-#define ENET_PLL_PLLDV_PREDIV		(2)
-#define ENET_PLL_PLLDV_MFD			(50)
-#define ENET_PLL_PLLDV_MFN			(0)
-
-#define DDR_PLL_PHI0_FREQ			(533000000)
-#define DDR_PLL_PHI1_FREQ			(1066000000)
-/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
-#define DDR_PLL_PHI1_DFS1_EN		(1)
-#define DDR_PLL_PHI1_DFS1_MFI		(2)
-#define DDR_PLL_PHI1_DFS1_MFN		(33)
-/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
-#define DDR_PLL_PHI1_DFS2_EN		(1)
-#define DDR_PLL_PHI1_DFS2_MFI		(2)
-#define DDR_PLL_PHI1_DFS2_MFN		(33)
-/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
-#define DDR_PLL_PHI1_DFS3_EN		(1)
-#define DDR_PLL_PHI1_DFS3_MFI		(3)
-#define DDR_PLL_PHI1_DFS3_MFN		(11)
-#define DDR_PLL_PHI1_DFS_Nr			(3)
-#define DDR_PLL_PLLDV_PREDIV		(2)
-#define DDR_PLL_PLLDV_MFD			(53)
-#define DDR_PLL_PLLDV_MFN			(6144)
-
-#define VIDEO_PLL_PHI0_FREQ			(600000000)
-#define VIDEO_PLL_PHI1_FREQ			(0)
-#define VIDEO_PLL_PHI1_DFS_Nr		(0)
-#define VIDEO_PLL_PLLDV_PREDIV		(1)
-#define VIDEO_PLL_PLLDV_MFD			(30)
-#define VIDEO_PLL_PLLDV_MFN			(0)
-
-#endif
-
-#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
deleted file mode 100644
index 1671af4adb..0000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
-
-#ifndef __ASSEMBLY__
-
-/* MC_ME registers definitions */
-
-/* MC_ME_GS */
-#define MC_ME_GS						(MC_ME_BASE_ADDR + 0x00000000)
-
-#define MC_ME_GS_S_SYSCLK_FIRC			(0x0 << 0)
-#define MC_ME_GS_S_SYSCLK_FXOSC			(0x1 << 0)
-#define MC_ME_GS_S_SYSCLK_ARMPLL		(0x2 << 0)
-#define MC_ME_GS_S_STSCLK_DISABLE		(0xF << 0)
-#define MC_ME_GS_S_FIRC					(1 << 4)
-#define MC_ME_GS_S_XOSC					(1 << 5)
-#define MC_ME_GS_S_ARMPLL				(1 << 6)
-#define MC_ME_GS_S_PERPLL				(1 << 7)
-#define MC_ME_GS_S_ENETPLL				(1 << 8)
-#define MC_ME_GS_S_DDRPLL				(1 << 9)
-#define MC_ME_GS_S_VIDEOPLL				(1 << 10)
-#define MC_ME_GS_S_MVR					(1 << 20)
-#define MC_ME_GS_S_PDO					(1 << 23)
-#define MC_ME_GS_S_MTRANS				(1 << 27)
-#define MC_ME_GS_S_CRT_MODE_RESET		(0x0 << 28)
-#define MC_ME_GS_S_CRT_MODE_TEST		(0x1 << 28)
-#define MC_ME_GS_S_CRT_MODE_DRUN		(0x3 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN0		(0x4 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN1		(0x5 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN2		(0x6 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN3		(0x7 << 28)
-
-/* MC_ME_MCTL */
-#define MC_ME_MCTL						(MC_ME_BASE_ADDR + 0x00000004)
-
-#define MC_ME_MCTL_KEY					(0x00005AF0)
-#define MC_ME_MCTL_INVERTEDKEY			(0x0000A50F)
-#define MC_ME_MCTL_RESET				(0x0 << 28)
-#define MC_ME_MCTL_TEST					(0x1 << 28)
-#define MC_ME_MCTL_DRUN					(0x3 << 28)
-#define MC_ME_MCTL_RUN0					(0x4 << 28)
-#define MC_ME_MCTL_RUN1					(0x5 << 28)
-#define MC_ME_MCTL_RUN2					(0x6 << 28)
-#define MC_ME_MCTL_RUN3					(0x7 << 28)
-
-/* MC_ME_ME */
-#define MC_ME_ME						(MC_ME_BASE_ADDR + 0x00000008)
-
-#define MC_ME_ME_RESET_FUNC				(1 << 0)
-#define MC_ME_ME_TEST					(1 << 1)
-#define MC_ME_ME_DRUN					(1 << 3)
-#define MC_ME_ME_RUN0					(1 << 4)
-#define MC_ME_ME_RUN1					(1 << 5)
-#define MC_ME_ME_RUN2					(1 << 6)
-#define MC_ME_ME_RUN3					(1 << 7)
-
-/* MC_ME_RUN_PCn */
-#define MC_ME_RUN_PCn(n)				(MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
-
-#define MC_ME_RUN_PCn_RESET				(1 << 0)
-#define MC_ME_RUN_PCn_TEST				(1 << 1)
-#define MC_ME_RUN_PCn_DRUN				(1 << 3)
-#define MC_ME_RUN_PCn_RUN0				(1 << 4)
-#define MC_ME_RUN_PCn_RUN1				(1 << 5)
-#define MC_ME_RUN_PCn_RUN2				(1 << 6)
-#define MC_ME_RUN_PCn_RUN3				(1 << 7)
-
-/*
- * MC_ME_RESET_MC/MC_ME_TEST_MC
- * MC_ME_DRUN_MC
- * MC_ME_RUNn_MC
- */
-#define MC_ME_RESET_MC						(MC_ME_BASE_ADDR + 0x00000020)
-#define MC_ME_TEST_MC						(MC_ME_BASE_ADDR + 0x00000024)
-#define MC_ME_DRUN_MC						(MC_ME_BASE_ADDR + 0x0000002C)
-#define MC_ME_RUNn_MC(n)					(MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
-
-#define MC_ME_RUNMODE_MC_SYSCLK(val)	(MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
-#define MC_ME_RUNMODE_MC_SYSCLK_MASK	(0x0000000F)
-#define MC_ME_RUNMODE_MC_FIRCON			(1 << 4)
-#define MC_ME_RUNMODE_MC_XOSCON			(1 << 5)
-#define MC_ME_RUNMODE_MC_PLL(pll)		(1 << (6 + (pll)))
-#define MC_ME_RUNMODE_MC_MVRON			(1 << 20)
-#define MC_ME_RUNMODE_MC_PDO			(1 << 23)
-#define MC_ME_RUNMODE_MC_PWRLVL0		(1 << 28)
-#define MC_ME_RUNMODE_MC_PWRLVL1		(1 << 29)
-#define MC_ME_RUNMODE_MC_PWRLVL2		(1 << 30)
-
-/* MC_ME_DRUN_SEC_CC_I */
-#define MC_ME_DRUN_SEC_CC_I					(MC_ME_BASE_ADDR + 0x260)
-/* MC_ME_RUNn_SEC_CC_I */
-#define MC_ME_RUNn_SEC_CC_I(n)				(MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)	((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET	(4)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET	(8)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET	(12)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK		(0x3)
-
-/*
- * ME_PCTLn
- * Please note that these registers are 8 bits width, so
- * the operations over them should be done using 8 bits operations.
- */
-#define MC_ME_PCTLn_RUNPCm(n)			( (n) & MC_ME_PCTLn_RUNPCm_MASK )
-#define MC_ME_PCTLn_RUNPCm_MASK			(0x7)
-
-/* DEC200 Peripheral Control Register		*/
-#define MC_ME_PCTL39	(MC_ME_BASE_ADDR + 0x000000E4)
-/* 2D-ACE Peripheral Control Register		*/
-#define MC_ME_PCTL40	(MC_ME_BASE_ADDR + 0x000000EB)
-/* ENET Peripheral Control Register		*/
-#define MC_ME_PCTL50	(MC_ME_BASE_ADDR + 0x000000F1)
-/* DMACHMUX0 Peripheral Control Register	*/
-#define MC_ME_PCTL49	(MC_ME_BASE_ADDR + 0x000000F2)
-/* CSI0 Peripheral Control Register			*/
-#define MC_ME_PCTL48	(MC_ME_BASE_ADDR + 0x000000F3)
-/* MMDC0 Peripheral Control Register		*/
-#define MC_ME_PCTL54	(MC_ME_BASE_ADDR + 0x000000F5)
-/* FRAY Peripheral Control Register			*/
-#define MC_ME_PCTL52	(MC_ME_BASE_ADDR + 0x000000F7)
-/* PIT0 Peripheral Control Register			*/
-#define MC_ME_PCTL58	(MC_ME_BASE_ADDR + 0x000000F9)
-/* FlexTIMER0 Peripheral Control Register	*/
-#define MC_ME_PCTL79	(MC_ME_BASE_ADDR + 0x0000010C)
-/* SARADC0 Peripheral Control Register		*/
-#define MC_ME_PCTL77	(MC_ME_BASE_ADDR + 0x0000010E)
-/* LINFLEX0 Peripheral Control Register		*/
-#define MC_ME_PCTL83	(MC_ME_BASE_ADDR + 0x00000110)
-/* IIC0 Peripheral Control Register			*/
-#define MC_ME_PCTL81	(MC_ME_BASE_ADDR + 0x00000112)
-/* DSPI0 Peripheral Control Register		*/
-#define MC_ME_PCTL87	(MC_ME_BASE_ADDR + 0x00000114)
-/* CANFD0 Peripheral Control Register		*/
-#define MC_ME_PCTL85	(MC_ME_BASE_ADDR + 0x00000116)
-/* CRC0 Peripheral Control Register			*/
-#define MC_ME_PCTL91	(MC_ME_BASE_ADDR + 0x00000118)
-/* DSPI2 Peripheral Control Register		*/
-#define MC_ME_PCTL89	(MC_ME_BASE_ADDR + 0x0000011A)
-/* SDHC Peripheral Control Register			*/
-#define MC_ME_PCTL93	(MC_ME_BASE_ADDR + 0x0000011E)
-/* VIU0 Peripheral Control Register			*/
-#define MC_ME_PCTL100	(MC_ME_BASE_ADDR + 0x00000127)
-/* HPSMI Peripheral Control Register		*/
-#define MC_ME_PCTL104	(MC_ME_BASE_ADDR + 0x0000012B)
-/* SIPI Peripheral Control Register			*/
-#define MC_ME_PCTL116	(MC_ME_BASE_ADDR + 0x00000137)
-/* LFAST Peripheral Control Register		*/
-#define MC_ME_PCTL120	(MC_ME_BASE_ADDR + 0x0000013B)
-/* MMDC1 Peripheral Control Register		*/
-#define MC_ME_PCTL162	(MC_ME_BASE_ADDR + 0x00000161)
-/* DMACHMUX1 Peripheral Control Register	*/
-#define MC_ME_PCTL161	(MC_ME_BASE_ADDR + 0x00000162)
-/* CSI1 Peripheral Control Register			*/
-#define MC_ME_PCTL160	(MC_ME_BASE_ADDR + 0x00000163)
-/* QUADSPI0 Peripheral Control Register		*/
-#define MC_ME_PCTL166	(MC_ME_BASE_ADDR + 0x00000165)
-/* PIT1 Peripheral Control Register			*/
-#define MC_ME_PCTL170	(MC_ME_BASE_ADDR + 0x00000169)
-/* FlexTIMER1 Peripheral Control Register	*/
-#define MC_ME_PCTL182	(MC_ME_BASE_ADDR + 0x00000175)
-/* IIC2 Peripheral Control Register			*/
-#define MC_ME_PCTL186	(MC_ME_BASE_ADDR + 0x00000179)
-/* IIC1 Peripheral Control Register			*/
-#define MC_ME_PCTL184	(MC_ME_BASE_ADDR + 0x0000017B)
-/* CANFD1 Peripheral Control Register		*/
-#define MC_ME_PCTL190	(MC_ME_BASE_ADDR + 0x0000017D)
-/* LINFLEX1 Peripheral Control Register		*/
-#define MC_ME_PCTL188	(MC_ME_BASE_ADDR + 0x0000017F)
-/* DSPI3 Peripheral Control Register		*/
-#define MC_ME_PCTL194	(MC_ME_BASE_ADDR + 0x00000181)
-/* DSPI1 Peripheral Control Register		*/
-#define MC_ME_PCTL192	(MC_ME_BASE_ADDR + 0x00000183)
-/* TSENS Peripheral Control Register		*/
-#define MC_ME_PCTL206	(MC_ME_BASE_ADDR + 0x0000018D)
-/* CRC1 Peripheral Control Register			*/
-#define MC_ME_PCTL204	(MC_ME_BASE_ADDR + 0x0000018F)
-/* VIU1 Peripheral Control Register		*/
-#define MC_ME_PCTL208	(MC_ME_BASE_ADDR + 0x00000193)
-/* JPEG Peripheral Control Register		*/
-#define MC_ME_PCTL212	(MC_ME_BASE_ADDR + 0x00000197)
-/* H264_DEC Peripheral Control Register	*/
-#define MC_ME_PCTL216	(MC_ME_BASE_ADDR + 0x0000019B)
-/* H264_ENC Peripheral Control Register	*/
-#define MC_ME_PCTL220	(MC_ME_BASE_ADDR + 0x0000019F)
-/* MBIST Peripheral Control Register	*/
-#define MC_ME_PCTL236	(MC_ME_BASE_ADDR + 0x000001A9)
-
-/* Core status register */
-#define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
-
-#endif
-
-#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
deleted file mode 100644
index 34501b2189..0000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
-
-#define MC_RGM_DES			(MC_RGM_BASE_ADDR)
-#define MC_RGM_FES			(MC_RGM_BASE_ADDR + 0x300)
-#define MC_RGM_FERD			(MC_RGM_BASE_ADDR + 0x310)
-#define MC_RGM_FBRE			(MC_RGM_BASE_ADDR + 0x330)
-#define MC_RGM_FESS			(MC_RGM_BASE_ADDR + 0x340)
-#define MC_RGM_DDR_HE			(MC_RGM_BASE_ADDR + 0x350)
-#define MC_RGM_DDR_HS			(MC_RGM_BASE_ADDR + 0x354)
-#define MC_RGM_FRHE			(MC_RGM_BASE_ADDR + 0x358)
-#define MC_RGM_FREC			(MC_RGM_BASE_ADDR + 0x600)
-#define MC_RGM_FRET			(MC_RGM_BASE_ADDR + 0x607)
-#define MC_RGM_DRET			(MC_RGM_BASE_ADDR + 0x60B)
-
-/* function reset sources mask */
-#define F_SWT4				0x8000
-#define F_JTAG				0x400
-#define F_FCCU_SOFT			0x40
-#define F_FCCU_HARD			0x20
-#define F_SOFT_FUNC			0x8
-#define F_ST_DONE			0x4
-#define F_EXT_RST			0x1
-
-#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h
deleted file mode 100644
index 8d74ae0266..0000000000
--- a/arch/arm/include/asm/arch-s32v234/mmdc.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
-#define __ARCH_ARM_MACH_S32V234_MMDC_H__
-
-#define MMDC0				0
-#define MMDC1				1
-
-#define MMDC_MDCTL			0x0
-#define MMDC_MDPDC			0x4
-#define MMDC_MDOTC			0x8
-#define MMDC_MDCFG0			0xC
-#define MMDC_MDCFG1			0x10
-#define MMDC_MDCFG2			0x14
-#define MMDC_MDMISC			0x18
-#define MMDC_MDSCR			0x1C
-#define MMDC_MDREF			0x20
-#define MMDC_MDRWD			0x2C
-#define MMDC_MDOR			0x30
-#define MMDC_MDMRR			0x34
-#define MMDC_MDCFG3LP		0x38
-#define MMDC_MDMR4			0x3C
-#define MMDC_MDASP			0x40
-#define MMDC_MAARCR			0x400
-#define MMDC_MAPSR			0x404
-#define MMDC_MAEXIDR0		0x408
-#define MMDC_MAEXIDR1		0x40C
-#define MMDC_MADPCR0		0x410
-#define MMDC_MADPCR1		0x414
-#define MMDC_MADPSR0		0x418
-#define MMDC_MADPSR1		0x41C
-#define MMDC_MADPSR2		0x420
-#define MMDC_MADPSR3		0x424
-#define MMDC_MADPSR4		0x428
-#define MMDC_MADPSR5		0x42C
-#define MMDC_MASBS0			0x430
-#define MMDC_MASBS1			0x434
-#define MMDC_MAGENP			0x440
-#define MMDC_MPZQHWCTRL		0x800
-#define MMDC_MPWLGCR		0x808
-#define MMDC_MPWLDECTRL0	0x80C
-#define MMDC_MPWLDECTRL1	0x810
-#define MMDC_MPWLDLST		0x814
-#define MMDC_MPODTCTRL		0x818
-#define MMDC_MPRDDQBY0DL	0x81C
-#define MMDC_MPRDDQBY1DL	0x820
-#define MMDC_MPRDDQBY2DL	0x824
-#define MMDC_MPRDDQBY3DL	0x828
-#define MMDC_MPDGCTRL0		0x83C
-#define MMDC_MPDGCTRL1		0x840
-#define MMDC_MPDGDLST0		0x844
-#define MMDC_MPRDDLCTL		0x848
-#define MMDC_MPRDDLST		0x84C
-#define MMDC_MPWRDLCTL		0x850
-#define MMDC_MPWRDLST		0x854
-#define MMDC_MPZQLP2CTL		0x85C
-#define MMDC_MPRDDLHWCTL	0x860
-#define MMDC_MPWRDLHWCTL	0x864
-#define MMDC_MPRDDLHWST0	0x868
-#define MMDC_MPRDDLHWST1	0x86C
-#define MMDC_MPWRDLHWST1	0x870
-#define MMDC_MPWRDLHWST2	0x874
-#define MMDC_MPWLHWERR		0x878
-#define MMDC_MPDGHWST0		0x87C
-#define MMDC_MPDGHWST1		0x880
-#define MMDC_MPDGHWST2		0x884
-#define MMDC_MPDGHWST3		0x888
-#define MMDC_MPPDCMPR1		0x88C
-#define MMDC_MPPDCMPR2		0x890
-#define MMDC_MPSWDAR0		0x894
-#define MMDC_MPSWDRDR0		0x898
-#define MMDC_MPSWDRDR1		0x89C
-#define MMDC_MPSWDRDR2		0x8A0
-#define MMDC_MPSWDRDR3		0x8A4
-#define MMDC_MPSWDRDR4		0x8A8
-#define MMDC_MPSWDRDR5		0x8AC
-#define MMDC_MPSWDRDR6		0x8B0
-#define MMDC_MPSWDRDR7		0x8B4
-#define MMDC_MPMUR0			0x8B8
-#define MMDC_MPDCCR			0x8C0
-
-#define MMDC_MPMUR0_FRC_MSR			(1 << 11)
-#define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h
deleted file mode 100644
index 7572581054..0000000000
--- a/arch/arm/include/asm/arch-s32v234/siul.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
-#define __ARCH_ARM_MACH_S32V234_SIUL_H__
-
-#include "ddr.h"
-
-#define SIUL2_MIDR1				(SIUL2_BASE_ADDR + 0x00000004)
-#define SIUL2_MIDR2				(SIUL2_BASE_ADDR + 0x00000008)
-#define SIUL2_DISR0				(SIUL2_BASE_ADDR + 0x00000010)
-#define SIUL2_DIRER0				(SIUL2_BASE_ADDR + 0x00000018)
-#define SIUL2_DIRSR0				(SIUL2_BASE_ADDR + 0x00000020)
-#define SIUL2_IREER0				(SIUL2_BASE_ADDR + 0x00000028)
-#define SIUL2_IFEER0				(SIUL2_BASE_ADDR + 0x00000030)
-#define SIUL2_IFER0				(SIUL2_BASE_ADDR + 0x00000038)
-
-#define SIUL2_IFMCR_BASE			(SIUL2_BASE_ADDR + 0x00000040)
-#define SIUL2_IFMCRn(i)				(SIUL2_IFMCR_BASE + 4 * (i))
-
-#define SIUL2_IFCPR				(SIUL2_BASE_ADDR + 0x000000C0)
-
-/* SIUL2_MSCR specifications as stated in Reference Manual:
- * 0 - 359 Output Multiplexed Signal Configuration Registers
- * 512- 1023 Input Multiplexed Signal Configuration Registers */
-#define SIUL2_MSCR_BASE				(SIUL2_BASE_ADDR + 0x00000240)
-#define SIUL2_MSCRn(i)				(SIUL2_MSCR_BASE + 4 * (i))
-
-#define SIUL2_IMCR_BASE				(SIUL2_BASE_ADDR + 0x00000A40)
-#define SIUL2_IMCRn(i)				(SIUL2_IMCR_BASE +  4 * (i))
-
-#define SIUL2_GPDO_BASE				(SIUL2_BASE_ADDR + 0x00001300)
-#define SIUL2_GPDOn(i)				(SIUL2_GPDO_BASE + 4 * (i))
-
-#define SIUL2_GPDI_BASE				(SIUL2_BASE_ADDR + 0x00001500)
-#define SIUL2_GPDIn(i)				(SIUL2_GPDI_BASE + 4 * (i))
-
-#define SIUL2_PGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001700)
-#define SIUL2_PGPDOn(i)				(SIUL2_PGPDO_BASE +  2 * (i))
-
-#define SIUL2_PGPDI_BASE			(SIUL2_BASE_ADDR + 0x00001740)
-#define SIUL2_PGPDIn(i)				(SIUL2_PGPDI_BASE + 2 * (i))
-
-#define SIUL2_MPGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001780)
-#define SIUL2_MPGPDOn(i)			(SIUL2_MPGPDO_BASE + 4 * (i))
-
-/* SIUL2_MSCR masks */
-#define SIUL2_MSCR_DDR_DO_TRIM(v)	((v) & 0xC0000000)
-#define SIUL2_MSCR_DDR_DO_TRIM_MIN	(0 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_50PS	(1 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_100PS	(2 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_150PS	(3 << 30)
-
-#define SIUL2_MSCR_DDR_INPUT(v)		((v) & 0x20000000)
-#define SIUL2_MSCR_DDR_INPUT_CMOS	(0 << 29)
-#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR	(1 << 29)
-
-#define SIUL2_MSCR_DDR_SEL(v)		((v) & 0x18000000)
-#define SIUL2_MSCR_DDR_SEL_DDR3		(0 << 27)
-#define SIUL2_MSCR_DDR_SEL_LPDDR2	(2 << 27)
-
-#define SIUL2_MSCR_DDR_ODT(v)		((v) & 0x07000000)
-#define SIUL2_MSCR_DDR_ODT_120ohm	(1 << 24)
-#define SIUL2_MSCR_DDR_ODT_60ohm	(2 << 24)
-#define SIUL2_MSCR_DDR_ODT_40ohm	(3 << 24)
-#define SIUL2_MSCR_DDR_ODT_30ohm	(4 << 24)
-#define SIUL2_MSCR_DDR_ODT_24ohm	(5 << 24)
-#define SIUL2_MSCR_DDR_ODT_20ohm	(6 << 24)
-#define SIUL2_MSCR_DDR_ODT_17ohm	(7 << 24)
-
-#define SIUL2_MSCR_DCYCLE_TRIM(v)	((v) & 0x00C00000)
-#define SIUL2_MSCR_DCYCLE_TRIM_NONE	(0 << 22)
-#define SIUL2_MSCR_DCYCLE_TRIM_LEFT	(1 << 22)
-#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT	(2 << 22)
-
-#define SIUL2_MSCR_OBE(v)		((v) & 0x00200000)
-#define SIUL2_MSCR_OBE_EN		(1 << 21)
-
-#define SIUL2_MSCR_ODE(v)		((v) & 0x00100000)
-#define SIUL2_MSCR_ODE_EN		(1 << 20)
-
-#define SIUL2_MSCR_IBE(v)		((v) & 0x00010000)
-#define SIUL2_MSCR_IBE_EN		(1 << 19)
-
-#define SIUL2_MSCR_HYS(v)		((v) & 0x00400000)
-#define SIUL2_MSCR_HYS_EN		(1 << 18)
-
-#define SIUL2_MSCR_INV(v)		((v) & 0x00020000)
-#define SIUL2_MSCR_INV_EN		(1 << 17)
-
-#define SIUL2_MSCR_PKE(v)		((v) & 0x00010000)
-#define SIUL2_MSCR_PKE_EN		(1 << 16)
-
-#define SIUL2_MSCR_SRE(v)		((v) & 0x0000C000)
-#define SIUL2_MSCR_SRE_SPEED_LOW_50	(0 << 14)
-#define SIUL2_MSCR_SRE_SPEED_LOW_100	(1 << 14)
-#define SIUL2_MSCR_SRE_SPEED_HIGH_100	(2 << 14)
-#define SIUL2_MSCR_SRE_SPEED_HIGH_200	(3 << 14)
-
-#define SIUL2_MSCR_PUE(v)		((v) & 0x00002000)
-#define SIUL2_MSCR_PUE_EN		(1 << 13)
-
-#define SIUL2_MSCR_PUS(v)		((v) & 0x00001800)
-#define SIUL2_MSCR_PUS_100K_DOWN	(0 << 11)
-#define SIUL2_MSCR_PUS_50K_DOWN		(1 << 11)
-#define SIUL2_MSCR_PUS_100K_UP		(2 << 11)
-#define SIUL2_MSCR_PUS_33K_UP		(3 << 11)
-
-#define SIUL2_MSCR_DSE(v)		((v) & 0x00000700)
-#define SIUL2_MSCR_DSE_240ohm		(1 << 8)
-#define SIUL2_MSCR_DSE_120ohm		(2 << 8)
-#define SIUL2_MSCR_DSE_80ohm		(3 << 8)
-#define SIUL2_MSCR_DSE_60ohm		(4 << 8)
-#define SIUL2_MSCR_DSE_48ohm		(5 << 8)
-#define SIUL2_MSCR_DSE_40ohm		(6 << 8)
-#define SIUL2_MSCR_DSE_34ohm		(7 << 8)
-
-#define SIUL2_MSCR_CRPOINT_TRIM(v)	((v) & 0x000000C0)
-#define SIUL2_MSCR_CRPOINT_TRIM_1	(1 << 6)
-
-#define SIUL2_MSCR_SMC(v)		((v) & 0x00000020)
-#define SIUL2_MSCR_MUX_MODE(v)		((v) & 0x0000000f)
-#define SIUL2_MSCR_MUX_MODE_ALT1	(0x1)
-#define SIUL2_MSCR_MUX_MODE_ALT2	(0x2)
-#define SIUL2_MSCR_MUX_MODE_ALT3	(0x3)
-
-/* UART settings */
-#define SIUL2_UART0_TXD_PAD	12
-#define SIUL2_UART_TXD		(SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |	\
-				SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
-
-#define SIUL2_UART0_MSCR_RXD_PAD	11
-#define SIUL2_UART0_IMCR_RXD_PAD	200
-
-#define SIUL2_UART_MSCR_RXD	(SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
-#define SIUL2_UART_IMCR_RXD	(SIUL2_MSCR_MUX_MODE_ALT2)
-
-/* uSDHC settings */
-#define SIUL2_USDHC_PAD_CTRL_BASE	(SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |	\
-						SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |		\
-						SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
-#define SIUL2_USDHC_PAD_CTRL_CMD	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
-#define SIUL2_USDHC_PAD_CTRL_CLK	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
-#define SIUL2_USDHC_PAD_CTRL_DAT0_3	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
-#define SIUL2_USDHC_PAD_CTRL_DAT4_7	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
-
-#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */