diff options
| author | Simon Glass <sjg@chromium.org> | 2018-12-10 10:37:41 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2018-12-13 16:36:30 -0700 |
| commit | 482e585bdf4a9eb1374d525ec4e57c671038d239 (patch) | |
| tree | 792c9c6ede73da31693c8c929cc8a52ec998d3e9 /arch/arm/mach-exynos/clock.c | |
| parent | cf9007ce88f412494d3b5438148d580c83f96685 (diff) | |
| download | u-boot-482e585bdf4a9eb1374d525ec4e57c671038d239.tar.gz | |
exynos: Add support for exynos5420 i2s pinmux
Allow setting the i2s pinmux correctly on exyno5420 so that i2c can be
used on that SoC. Also rename EXYNOS_AUDSS to something consistent with
other naming.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-exynos/clock.c')
| -rw-r--r-- | arch/arm/mach-exynos/clock.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 2425a72866..73aa4cdad3 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -1317,6 +1317,19 @@ int exynos5_set_epll_clk(unsigned long rate) return 0; } +static int exynos5420_set_i2s_clk_source(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + + setbits_le32(&clk->src_top6, EXYNOS5420_CLK_SRC_MOUT_EPLL); + clrsetbits_le32(&clk->src_mau, EXYNOS5420_AUDIO0_SEL_MASK, + (EXYNOS5420_CLK_SRC_SCLK_EPLL)); + setbits_le32(EXYNOS5_AUDIOSS_BASE, 1 << 0); + + return 0; +} + int exynos5_set_i2s_clk_source(unsigned int i2s_id) { struct exynos5_clock *clk = @@ -1758,8 +1771,12 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, int set_i2s_clk_source(unsigned int i2s_id) { - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_source(i2s_id); + if (cpu_is_exynos5()) { + if (proid_is_exynos542x()) + return exynos5420_set_i2s_clk_source(); + else + return exynos5_set_i2s_clk_source(i2s_id); + } return 0; } |