diff options
| author | Marek Vasut <marex@denx.de> | 2020-08-05 15:34:05 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-08-17 17:54:01 +0200 |
| commit | 5ec83561c42cddd0f78a1e183b937f44902a18e4 (patch) | |
| tree | 88bdcc2187ad28c8898ac65c01d251a1ddf44826 /arch/arm/mach-imx/init.c | |
| parent | c72372d38cb9d625f32f32e95e8fe821e5e2734b (diff) | |
| download | u-boot-5ec83561c42cddd0f78a1e183b937f44902a18e4.tar.gz | |
ARM: imx: Add support for switching primary/secondary boot mode to bmode
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the user.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/mach-imx/init.c')
| -rw-r--r-- | arch/arm/mach-imx/init.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/init.c b/arch/arm/mach-imx/init.c index e30d63b896..ce3eb4b0b8 100644 --- a/arch/arm/mach-imx/init.c +++ b/arch/arm/mach-imx/init.c @@ -104,20 +104,28 @@ void init_src(void) void boot_mode_apply(unsigned cfg_val) { #ifdef CONFIG_MX6 + const u32 persist_sec = IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT; const u32 bmode = IMX6_SRC_GPR10_BMODE; #elif CONFIG_MX7 + const u32 persist_sec = IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT; const u32 bmode = IMX7_SRC_GPR10_BMODE; #endif struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg; - writel(cfg_val, &psrc->gpr9); - reg = readl(&psrc->gpr10); - if (cfg_val) - reg |= bmode; - else - reg &= ~bmode; - writel(reg, &psrc->gpr10); + if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT) + clrbits_le32(&psrc->gpr10, persist_sec); + else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT) + setbits_le32(&psrc->gpr10, persist_sec); + else { + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= bmode; + else + reg &= ~bmode; + writel(reg, &psrc->gpr10); + } } #endif |