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authorPeng Fan <peng.fan@nxp.com>2019-08-27 06:25:37 +0000
committerStefano Babic <sbabic@denx.de>2019-10-08 16:36:36 +0200
commit0528ba0e1c4f879278d597b1aeaf1bf31a943f75 (patch)
treecf76ca46717096a3a3baf1f556096d6ce7903c1a /arch/arm/mach-imx
parentb3cf0a8f03d162e030cde1131751d060853e16fc (diff)
downloadu-boot-0528ba0e1c4f879278d597b1aeaf1bf31a943f75.tar.gz
imx8m: soc: enable SCTR clock before timer init
To i.MX8MM SCTR clock is disabled by ROM, so before timer init need to enable it. To i.MX8MQ, it does not hurt the clock is enabled again. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a33ca35653..ac80266010 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -232,6 +232,12 @@ int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
+ * ROM might disable clock for SCTR,
+ * enable the clock before timer_init.
+ */
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ clock_enable(CCGR_SCTR, 1);
+ /*
* Init timer at very early state, because sscg pll setting
* will use it
*/