diff options
author | Tom Rini <trini@konsulko.com> | 2020-01-20 14:54:55 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2020-01-20 14:54:55 -0500 |
commit | 07add22cab3be86067c227a30ad5d0feab541316 (patch) | |
tree | 9731f3a2a402d60f5a0d93fee6856d9fd1dc87b7 /arch/arm/mach-k3/j721e_init.c | |
parent | cd304e218012de4ac2e3d55e869b2102af4fdcb2 (diff) | |
parent | 1adea9cc03a73d43a8f5c88659fa163fe21b382b (diff) | |
download | u-boot-07add22cab3be86067c227a30ad5d0feab541316.tar.gz |
Merge tag '2020-01-20-ti-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-tiWIP/20Jan2020
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes
K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support
DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti
AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
Diffstat (limited to 'arch/arm/mach-k3/j721e_init.c')
-rw-r--r-- | arch/arm/mach-k3/j721e_init.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 4758739266..f7f7398081 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -20,6 +20,47 @@ #include <dm/pinctrl.h> #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2560, 8 }, + { "PCIE1_CFG", 2561, 8 }, + { "USB3SS0_CORE", 2568, 4 }, + { "USB3SS1_CORE", 2570, 4 }, + { "EMMC8SS0_CFG", 2576, 4 }, + { "UFS_HCI0_CFG", 2580, 4 }, + { "SERDES0", 2584, 1 }, + { "SERDES1", 2585, 1 }, +}, cbass_hc0_fwls[] = { + { "PCIE0_HP", 2528, 24 }, + { "PCIE0_LP", 2529, 24 }, + { "PCIE1_HP", 2530, 24 }, + { "PCIE1_LP", 2531, 24 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2380, 4 }, +}, cbass_rc0_fwls[] = { + { "GPMC0", 2310, 8 }, +}, infra_cbass0_fwls[] = { + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 2 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_CTRL_MMR0", 131, 16 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -114,11 +155,25 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); #endif + /* Perform EEPROM-based board detection */ + do_board_detect(); + #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), &dev); |