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authorLokesh Vutla <lokeshvutla@ti.com>2018-11-02 19:51:03 +0530
committerTom Rini <trini@konsulko.com>2018-11-16 16:51:58 -0500
commit23f7b1a77602d335811aea80af1cacf5bff502af (patch)
tree189fd738a698c084c535e185a88d92be717e921e /arch/arm/mach-k3/r5_mpu.c
parent06bda1259ffc3ef899de70c7fb86b0982a2912f0 (diff)
downloadu-boot-23f7b1a77602d335811aea80af1cacf5bff502af.tar.gz
armv7R: K3: am654: Enable MPU regions
Enable MPU regions for AM654 evm: - Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable - Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc - Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc - region3-15: Disabled With this dcache can be enabled either in SPL or U-Boot. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-k3/r5_mpu.c')
-rw-r--r--arch/arm/mach-k3/r5_mpu.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
new file mode 100644
index 0000000000..ee076ed877
--- /dev/null
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: R5 MPU region definitions
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/kernel.h>
+#include "common.h"
+
+struct mpu_region_config k3_mpu_regions[16] = {
+ /*
+ * Make all 4GB as Device Memory and not executable. We are overriding
+ * it with next region for any requirement.
+ */
+ {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
+ REGION_4GB},
+
+ /* SPL code area marking it as WB and Write allocate. */
+ {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_8MB},
+
+ /* U-Boot's code area marking it as WB and Write allocate */
+ {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_2GB},
+ {0x0, 3, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 4, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 5, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 6, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 7, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 8, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 9, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 10, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 11, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 12, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 13, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 14, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 15, 0x0, 0x0, 0x0, 0x0},
+};
+
+void setup_k3_mpu_regions(void)
+{
+ setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
+}