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| author | Kever Yang <kever.yang@rock-chips.com> | 2019-07-22 20:02:02 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-29 10:26:28 +0800 |
| commit | 5eb9a78fcdb3af09527f16698f251756eb07359f (patch) | |
| tree | 015a69a4ac0bcac6a85824aeb0bef110646c2f28 /arch/arm/mach-rockchip/sdram_common.c | |
| parent | 54f17fa05d453618afabff1246c1a16cea304b1b (diff) | |
| download | u-boot-5eb9a78fcdb3af09527f16698f251756eb07359f.tar.gz | |
rockchip: sdram_common: add common dram_init_banksize
dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-rockchip/sdram_common.c')
| -rw-r--r-- | arch/arm/mach-rockchip/sdram_common.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 8684dbd4fa..22a4aca940 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -11,6 +11,69 @@ #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; + +#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024) + +struct tos_parameter_t { + u32 version; + u32 checksum; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } tee_mem; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } drm_mem; + s64 reserve[8]; +}; + +int dram_init_banksize(void) +{ + size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + gd->ram_top); + +#ifdef CONFIG_ARM64 + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#else +#ifdef CONFIG_SPL_OPTEE + struct tos_parameter_t *tos_parameter; + + tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + TRUST_PARAMETER_OFFSET); + + if (tos_parameter->tee_mem.flags == 1) { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + - CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + tos_parameter->tee_mem.size; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 32M for OPTEE with TA */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0x2000000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } +#else + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#endif +#endif + + return 0; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; |