diff options
| author | Ramon Fried <ramon.fried@gmail.com> | 2018-05-16 12:13:39 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-26 18:19:11 -0400 |
| commit | 640dc349422d1f228ef8d2bb35cd89b1663273f1 (patch) | |
| tree | f195699e78d77164749bc509e47101e49072ea79 /arch/arm/mach-snapdragon/clock-snapdragon.h | |
| parent | 7e5ad796bcd65772a87da236ae21cd536ae3a4d2 (diff) | |
| download | u-boot-640dc349422d1f228ef8d2bb35cd89b1663273f1.tar.gz | |
mach-snapdragon: Fix UART clock flow
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Diffstat (limited to 'arch/arm/mach-snapdragon/clock-snapdragon.h')
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-snapdragon.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2cff4f8a06..58fab40a2e 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -11,13 +11,18 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_MASK (7 << 8) -struct gpll0_ctrl { +struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; int vote_bit; }; +struct vote_clk { + uintptr_t cbcr_reg; + uintptr_t ena_vote; + int vote_bit; +}; struct bcr_regs { uintptr_t cfg_rcgr; uintptr_t cmd_rcgr; @@ -30,9 +35,10 @@ struct msm_clk_priv { phys_addr_t base; }; -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0); +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source); |