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authorMarek Vasut <marex@denx.de>2018-05-12 00:09:21 +0200
committerMarek Vasut <marex@denx.de>2018-05-18 10:30:46 +0200
commit480f7f9c3ee2f8a83603cf07ba8d86a95f3c265c (patch)
treee8d4d31042dc375b07a1bf0f25f767ba2c337022 /arch/arm/mach-socfpga/include
parent73172753f4f3351ed1c9d2f6586fc599ce4e728c (diff)
downloadu-boot-480f7f9c3ee2f8a83603cf07ba8d86a95f3c265c.tar.gz
ARM: socfpga: Sync A10 clock manager binding parser
The A10 clock manager parsed DT bindings generated by Quartus the bsp-editor to configure the A10 clocks. Sadly, those DT bindings changed at some point. The clock manager patch used the old ones, this patch replaces the bindings parser with one for the new set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga/include')
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index a3289ee2da..cb2306e5bc 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -107,7 +107,7 @@ unsigned int cm_get_spi_controller_clk_hz(void);
#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
-#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
+#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
/* value */