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author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 10:38:21 +0800 |
---|---|---|
committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
commit | 94172c7961124a4abf1aeedb1705a88a77744103 (patch) | |
tree | 1a6756077070c3dba1861bceb1af27ad5a17b0f3 /arch/arm/mach-socfpga/misc.c | |
parent | db5741f7a85ec3ee79b64496172afaa7dc2cb225 (diff) | |
download | u-boot-94172c7961124a4abf1aeedb1705a88a77744103.tar.gz |
arm: socfpga: Convert clock manager from struct to defines
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
-rw-r--r-- | arch/arm/mach-socfpga/misc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 1ef02a13bf..b86ff962a8 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; +phys_addr_t socfpga_clkmgr_base __section(".data"); phys_addr_t socfpga_rstmgr_base __section(".data"); phys_addr_t socfpga_sysmgr_base __section(".data"); @@ -243,6 +244,10 @@ void socfpga_get_managers_addr(void) ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); if (ret) hang(); + + ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); + if (ret) + hang(); } phys_addr_t socfpga_get_rstmgr_addr(void) @@ -254,3 +259,8 @@ phys_addr_t socfpga_get_sysmgr_addr(void) { return socfpga_sysmgr_base; } + +phys_addr_t socfpga_get_clkmgr_addr(void) +{ + return socfpga_clkmgr_base; +} |