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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 10:38:19 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | bb25aca1343304e0334e9eebfb9d350eaf276882 (patch) | |
| tree | 00e8e1c3b79e4a6175bfeccf716d106ec02593cc /arch/arm/mach-socfpga/reset_manager_s10.c | |
| parent | dd72cbd9e91dfa80f04a5921546d19e189bb2361 (diff) | |
| download | u-boot-bb25aca1343304e0334e9eebfb9d350eaf276882.tar.gz | |
arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager_s10.c')
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 499a84aff5..8af28ee410 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -12,31 +12,31 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { - const void *reg; + unsigned long reg; if (RSTMGR_BANK(reset) == 0) - reg = &reset_manager_base->mpumodrst; + reg = RSTMGR_S10_MPUMODRST; else if (RSTMGR_BANK(reset) == 1) - reg = &reset_manager_base->per0modrst; + reg = RSTMGR_S10_PER0MODRST; else if (RSTMGR_BANK(reset) == 2) - reg = &reset_manager_base->per1modrst; + reg = RSTMGR_S10_PER1MODRST; else if (RSTMGR_BANK(reset) == 3) - reg = &reset_manager_base->brgmodrst; + reg = RSTMGR_S10_BRGMODRST; else /* Invalid reset register, do nothing */ return; if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + setbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); + clrbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); } /* @@ -50,9 +50,9 @@ void socfpga_per_reset_all(void) /* disable all except OCP and l4wd0. OCP disable later */ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), - &reset_manager_base->per0modrst); - writel(~l4wd0, &reset_manager_base->per0modrst); - writel(0xffffffff, &reset_manager_base->per1modrst); + socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST); + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST); + writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST); } void socfpga_bridges_reset(int enable) @@ -62,7 +62,8 @@ void socfpga_bridges_reset(int enable) setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); /* Release all bridges from reset state */ - clrbits_le32(&reset_manager_base->brgmodrst, ~0); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST, + ~0); /* Poll until all idleack to 0 */ while (readl(&system_manager_base->noc_idleack)) @@ -85,9 +86,9 @@ void socfpga_bridges_reset(int enable) ; /* Reset all bridges (except NOR DDR scheduler & F2S) */ - setbits_le32(&reset_manager_base->brgmodrst, + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST, ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + RSTMGR_BRGMODRST_FPGA2SOC_MASK)); /* Disable NOC timeout */ writel(0, &system_manager_base->noc_timeout); @@ -99,6 +100,6 @@ void socfpga_bridges_reset(int enable) */ int cpu_has_been_warmreset(void) { - return readl(&reset_manager_base->status) & - RSTMGR_L4WD_MPU_WARMRESET_MASK; + return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; } |