diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-02-28 17:15:00 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-13 21:45:37 -0400 |
| commit | f5bd13ed57730fd6e0de274aa52e4faef79871e9 (patch) | |
| tree | d70d6691602db2aca4f2f6c8aab3a6c855ff0f42 /arch/arm/mach-stm32 | |
| parent | 227cefe02c77d1aeebc9a4993635ff62d48a0f6f (diff) | |
| download | u-boot-f5bd13ed57730fd6e0de274aa52e4faef79871e9.tar.gz | |
mach-stm32: Use default memory map as background region
On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires
uncachable regions. These regions are defined in DT.
Since kernel linux v4.15, on ARMv7-M Cortex, kernel is able
to configure MPU regions depending on DT settings.
As kernel is able to configure MPU, this allows to remove
MPU region settings in bootloader.
On Cortex M processors, MPU allows to use a default memory map.
(see B3.5.4 MPU Control Register, MPU_CTRL in
https://developer.arm.com/products/architecture/m-profile/docs/ddi0403/latest/armv7-m-architecture-reference-manual)
Use the default memory map as background region for all STM32 SoCs
family with an additional MPU region corresponding to the SDRAM area.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/mach-stm32')
| -rw-r--r-- | arch/arm/mach-stm32/soc.c | 36 |
1 files changed, 11 insertions, 25 deletions
diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index df20d547c5..f6fd0b2e23 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -15,35 +15,21 @@ int arch_cpu_init(void) struct mpu_region_config stm32_region_config[] = { /* - * Make all 4GB cacheable & executable. We are overriding it - * with next region for any requirement. e.g. below region1, - * 2 etc. - * In other words, the area not coming in following - * regions configuration is the one configured here in region_0 - * (cacheable & executable). + * Make SDRAM area cacheable & executable. */ +#if defined(CONFIG_STM32F4) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_4GB }, - - /* armv7m code area */ - { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - - /* Device area : Not executable */ - { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, + O_I_WB_RD_WR_ALLOC, REGION_16MB }, +#endif - /* - * Armv7m fixed configuration: strongly ordered & not - * executable, not cacheable - */ - { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, +#if defined(CONFIG_STM32F7) + { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_16MB }, +#endif -#if !defined(CONFIG_STM32H7) - /* Device area : Not executable */ - { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, +#if defined(CONFIG_STM32H7) + { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_32MB }, #endif }; |