diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 20:07:40 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 22:42:00 +0900 |
| commit | d41b358fb331c2907f1f217686d38eeaf17eece4 (patch) | |
| tree | 9d8ea673b2beca4fab63764e762f74c455021e62 /arch/arm/mach-uniphier/clk | |
| parent | c3d8f1e8e92fd70abb912942300cf44fff9e9d86 (diff) | |
| download | u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.tar.gz | |
ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.
Turn the SG_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/clk-ld11.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-ld4.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-pro4.c | 2 |
3 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index e997acf1b7..0917b33c25 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -17,16 +17,16 @@ void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ - if ((readl(SG_PINMON0) & BIT(27)) && + if ((readl(sg_base + SG_PINMON0) & BIT(27)) && uniphier_boot_device_raw() != BOOT_DEVICE_USB) { - writel(1, SG_ETPHYPSHUT); - writel(1, SG_ETPHYCNT); + writel(1, sg_base + SG_ETPHYPSHUT); + writel(1, sg_base + SG_ETPHYCNT); udelay(1); /* wait for regulator level 1.1V -> 2.5V */ - writel(3, SG_ETPHYCNT); - writel(3, SG_ETPHYPSHUT); - writel(7, SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYPSHUT); + writel(7, sg_base + SG_ETPHYCNT); } /* TODO: use "mmc-pwrseq-emmc" */ @@ -37,7 +37,7 @@ void uniphier_ld11_clk_init(void) int ch; for (ch = 0; ch < 3; ch++) { - void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; + void __iomem *phyctrl = sg_base + SG_USBPHYCTRL; writel(0x82280600, phyctrl + 8 * ch); writel(0x00000106, phyctrl + 8 * ch + 4); diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 6a145a3baa..34f1c9cc28 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -16,7 +16,7 @@ static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; @@ -56,7 +56,7 @@ static void vpll_init(void) { u32 tmp, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index 2ee2ed6bd6..312a5fcfdf 100644 --- a/arch/arm/mach-uniphier/clk/pll-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -17,7 +17,7 @@ static void vpll_init(void) u32 tmp, clk_mode_axosel; /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ |