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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-08-29 13:10:38 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:13:11 -0700 |
| commit | e982746844605e5155fbd2e0ce13c3ecf7fafe48 (patch) | |
| tree | 2889b68a69a0976bca54441caa9fe6839451ac56 /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | 0e61077b215aff9228a4d6ca746761b49380713c (diff) | |
| download | u-boot-e982746844605e5155fbd2e0ce13c3ecf7fafe48.tar.gz | |
powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
- e6500 core has L2 cluster (Kibo)
- e5500 core has Backside L2 Cache
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d329aa84ab..6a81fa73e4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -699,7 +699,7 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR |