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authorStefano Babic <sbabic@denx.de>2020-05-10 13:03:56 +0200
committerStefano Babic <sbabic@denx.de>2020-05-10 13:03:56 +0200
commitb77d0292ca9f3ca69259dca7e2c5e193a403b289 (patch)
tree0af352de3e405f839188aad7acaa9930d18afdd8 /arch/powerpc/dts/p1010si-post.dtsi
parent8142a97d541ef1473925b3677d6bf86bcddb69ac (diff)
parentc5c657644bc35fd6b3d6e5517698721e90646b8d (diff)
downloadu-boot-b77d0292ca9f3ca69259dca7e2c5e193a403b289.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/powerpc/dts/p1010si-post.dtsi')
-rw-r--r--arch/powerpc/dts/p1010si-post.dtsi48
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
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+++ b/arch/powerpc/dts/p1010si-post.dtsi
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+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1010-immr", "simple-bus";
+ bus-frequency = <0>;
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+};
+
+/* controller at 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};