diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-08-20 09:35:28 +0000 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-26 21:23:21 +0530 |
| commit | ec70cedbceaee6c418fde79530a2761b94d0d94b (patch) | |
| tree | 2c84fcfce4c2808e9f0d5933fae68a160dd22dea /arch/powerpc/dts/p1020-post.dtsi | |
| parent | fa3602859f795d3dda1c625052105bf6aea22b20 (diff) | |
| download | u-boot-ec70cedbceaee6c418fde79530a2761b94d0d94b.tar.gz | |
powerpc: Enable device tree support for P1020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/p1020-post.dtsi')
| -rw-r--r-- | arch/powerpc/dts/p1020-post.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi new file mode 100644 index 0000000000..e1a4f500a6 --- /dev/null +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1020-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; |