x86: broadwell: Allow SDRAM init from SPL

At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

1 files changed, 0 insertions, 93 deletions

diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 1b9f9840c6..b8450cc9d2 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -34,99 +34,6 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void broadwell_fill_pei_data(struct pei_data *pei_data)
-{
-	pei_data->pei_version = PEI_VERSION;
-	pei_data->board_type = BOARD_TYPE_ULT;
-	pei_data->pciexbar = MCFG_BASE_ADDRESS;
-	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
-	pei_data->ehcibar = EARLY_EHCI_BAR;
-	pei_data->xhcibar = EARLY_XHCI_BAR;
-	pei_data->gttbar = EARLY_GTT_BAR;
-	pei_data->pmbase = ACPI_BASE_ADDRESS;
-	pei_data->gpiobase = GPIO_BASE_ADDRESS;
-	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
-	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
-	pei_data->tx_byte = sdram_console_tx_byte;
-	pei_data->ddr_refresh_2x = 1;
-}
-
-static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
-				      uint16_t length, uint8_t enable,
-				      uint8_t oc_pin, uint8_t location)
-{
-	pei_data->usb2_ports[port].length   = length;
-	pei_data->usb2_ports[port].enable   = enable;
-	pei_data->usb2_ports[port].oc_pin   = oc_pin;
-	pei_data->usb2_ports[port].location = location;
-}
-
-static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
-				      uint8_t enable, uint8_t oc_pin,
-				      uint8_t fixed_eq)
-{
-	pei_data->usb3_ports[port].enable   = enable;
-	pei_data->usb3_ports[port].oc_pin   = oc_pin;
-	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
-}
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
-	/* DQ byte map for Samus board */
-	const u8 dq_map[2][6][2] = {
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
-	/* DQS CPU<>DRAM map for Samus board */
-	const u8 dqs_map[2][8] = {
-		{ 2, 0, 1, 3, 6, 4, 7, 5 },
-		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
-
-	pei_data->ec_present = 1;
-
-	/* One installed DIMM per channel */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
-	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
-	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-
-	/* P0: HOST PORT */
-	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
-			   USB_PORT_BACK_PANEL);
-	/* P1: HOST PORT */
-	pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
-			   USB_PORT_BACK_PANEL);
-	/* P2: RAIDEN */
-	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_BACK_PANEL);
-	/* P3: SD CARD */
-	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-	/* P4: RAIDEN */
-	pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_BACK_PANEL);
-	/* P5: WWAN (Disabled) */
-	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
-			   USB_PORT_SKIP);
-	/* P6: CAMERA */
-	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-	/* P7: BT */
-	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-
-	/* P1: HOST PORT */
-	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
-	/* P2: HOST PORT */
-	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
-	/* P3: RAIDEN */
-	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
-	/* P4: RAIDEN */
-	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
-}
-
 static unsigned long get_top_of_ram(struct udevice *dev)
 {
 	/*