diff options
| author | Simon Glass <sjg@chromium.org> | 2019-09-25 08:56:37 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-10-08 13:57:47 +0800 |
| commit | 55a6b13a75276fbdf7186b34b4ad72238a7ec16b (patch) | |
| tree | 9efd23735408507ff6fd90df3f27ebcdc6888607 /arch/x86/cpu/ivybridge | |
| parent | 246ac08b037befab08805750049df75044ab7f6c (diff) | |
| download | u-boot-55a6b13a75276fbdf7186b34b4ad72238a7ec16b.tar.gz | |
x86: Use a common bus clock for Intel CPUs
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in
a common file and tidy up the copies.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
| -rw-r--r-- | arch/x86/cpu/ivybridge/model_206ax.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index ed66d2dd8d..3177ba3297 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -346,7 +346,7 @@ static void set_max_ratio(void) msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); } static void set_energy_perf_bias(u8 policy) @@ -418,7 +418,7 @@ static int model_206ax_init(struct udevice *dev) static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) { - return cpu_intel_get_info(info, SANDYBRIDGE_BCLK); + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); return 0; } |