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| author | Sean Anderson <seanga2@gmail.com> | 2020-09-21 07:51:35 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-09-30 08:54:52 +0800 |
| commit | c41045411bbb64eeda2d404b79723f8d2802351c (patch) | |
| tree | 40ebad26d3f1f4ba783280522898cfc5b23b3761 /arch | |
| parent | 422c3c5edf41318a3cdb532111148f085bc33638 (diff) | |
| download | u-boot-c41045411bbb64eeda2d404b79723f8d2802351c.tar.gz | |
Revert "riscv: Clear pending interrupts before enabling IPIs"
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.
The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.
This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/start.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..e3222b1ea7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,8 +65,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif |