diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2018-03-20 10:54:52 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-04-06 20:45:28 -0400 |
| commit | 0ed232b15386616d186b67a3689e149581dcf2b7 (patch) | |
| tree | e7d48b767ca22f2754413e569f55d8de8d045aa9 /arch | |
| parent | 35a66960cd7358588bd678b4b3dfedb27226fe3e (diff) | |
| download | u-boot-0ed232b15386616d186b67a3689e149581dcf2b7.tar.gz | |
stm32mp1: add eMMC support for ED1
Add command GPT support
Add EMMC boot support
Add the 2 other SDMMC instances for ED1:
- SDMMC2 = mmc 1, eMMC on the ED1 board
- SDMMC3 = extension connector, deactivated by default
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/stm32mp157.dtsi | 28 | ||||
| -rw-r--r-- | arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 21 | ||||
| -rw-r--r-- | arch/arm/dts/stm32mp157c-ed1.dts | 37 |
3 files changed, 86 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index 32d3984259..77953c8e9d 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -86,6 +86,20 @@ status = "disabled"; }; + sdmmc3: sdmmc@48004000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x48004000 0x400>, <0x48005000 0x400>; + reg-names = "sdmmc", "delay"; + interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; + clocks = <&rcc_clk SDMMC3_K>; + resets = <&rcc_rst SDMMC3_R>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "syscon", "simple-mfd"; @@ -288,6 +302,20 @@ status = "disabled"; }; + sdmmc2: sdmmc@58007000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + reg-names = "sdmmc", "delay"; + interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; + clocks = <&rcc_clk SDMMC2_K>; + resets = <&rcc_rst SDMMC2_R>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + i2c4: i2c@5c002000 { compatible = "st,stm32f7-i2c"; reg = <0x5c002000 0x400>; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 94d27fb398..5d43753804 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -11,6 +11,7 @@ / { aliases { mmc0 = &sdmmc1; + mmc1 = &sdmmc2; i2c3 = &i2c4; }; }; @@ -77,6 +78,7 @@ CLK_SDMMC12_PLL3R CLK_I2C46_PCLK5 CLK_I2C12_PCLK1 + CLK_SDMMC3_PLL3R CLK_I2C35_PCLK1 CLK_UART1_PCLK5 CLK_UART24_PCLK1 @@ -131,3 +133,22 @@ &sdmmc1 { u-boot,dm-spl; }; + +/* MMC2 boot */ +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 4b20fabb71..129cd02418 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -112,6 +112,31 @@ bias-pull-up; }; }; + sdmmc2_b4_pins_a: sdmmc2-b4@0 { + pins { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_pins_a: sdmmc2-d47@0 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + }; }; &pinctrl_z { @@ -160,6 +185,18 @@ status = "okay"; }; +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + non-removable; + no-sd; + no-sdio; + st,dirpol; + st,negedge; + bus-width = <8>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; |