Merge git://git.denx.de/u-boot-sunxi

Signed-off-by: Tom Rini <trini@konsulko.com>

14 files changed, 147 insertions, 74 deletions

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
index 9c61beac01..32a263ce3d 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
@@ -4,25 +4,38 @@
 	};
 
 	soc {
-		emac: ethernet@01c30000 {
+		syscon: syscon@1c00000 {
+			compatible = "allwinner,sun50i-a64-system-controller",
+				     "syscon";
+			reg = <0x01c00000 0x1000>;
+		};
+
+		emac: ethernet@1c30000 {
 			compatible = "allwinner,sun50i-a64-emac";
-			reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
-			reg-names = "emac", "syscon";
+			syscon = <&syscon>;
+			reg = <0x01c30000 0x10000>;
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
 			resets = <&ccu RST_BUS_EMAC>;
-			reset-names = "ahb";
+			reset-names = "stmmaceth";
 			clocks = <&ccu CLK_BUS_EMAC>;
-			clock-names = "ahb";
+			clock-names = "stmmaceth";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&rgmii_pins>;
 			phy-mode = "rgmii";
-			phy = <&phy1>;
+			phy-handle = <&ext_rgmii_phy>;
 			status = "okay";
 
-			phy1: ethernet-phy@1 {
-				reg = <1>;
+			mdio: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ext_rgmii_phy: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
 			};
 		};
 	};
@@ -30,21 +43,17 @@
 
 &pio {
 	rmii_pins: rmii_pins {
-		allwinner,pins = "PD10", "PD11", "PD13", "PD14",
-				 "PD17", "PD18", "PD19", "PD20",
-				 "PD22", "PD23";
-		allwinner,function = "emac";
-		allwinner,drive = <3>;
-		allwinner,pull = <0>;
+		pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+		       "PD18", "PD19", "PD20", "PD22", "PD23";
+		function = "emac";
+		drive-strength = <40>;
 	};
 
 	rgmii_pins: rgmii_pins {
-		allwinner,pins = "PD8", "PD9", "PD10", "PD11",
-				 "PD12", "PD13", "PD15",
-				 "PD16", "PD17", "PD18", "PD19",
-				 "PD20", "PD21", "PD22", "PD23";
-		allwinner,function = "emac";
-		allwinner,drive = <3>;
-		allwinner,pull = <0>;
+		pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+		       "PD13", "PD15", "PD16", "PD17", "PD18",
+		       "PD19", "PD20", "PD21", "PD22", "PD23";
+		function = "emac";
+		drive-strength = <40>;
 	};
 };
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index 780d59a096..d1c347d2b8 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -108,10 +108,13 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_rgmii_pins>;
 	phy-mode = "rgmii";
-	phy = <&phy1>;
+	phy-handle = <&ext_rgmii_phy>;
 	status = "okay";
+};
 
-	phy1: ethernet-phy@1 {
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
 		reg = <1>;
 	};
 };
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
index ea50dda75a..ffd21487dc 100644
--- a/arch/arm/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/dts/sun8i-a23-a33.dtsi
@@ -289,6 +289,23 @@
 				function = "uart1";
 			};
 
+			nand_pins_a: nand-base0@0 {
+				pins = "PC0", "PC1", "PC2", "PC5",
+				       "PC8", "PC9", "PC10", "PC11",
+				       "PC12", "PC13", "PC14", "PC15";
+				function = "nand0";
+			};
+
+			nand_cs0_pins_a: nand-cs@0 {
+				pins = "PC4";
+				function = "nand0";
+			};
+
+			nand_rb0_pins_a: nand-rb@0 {
+				pins = "PC6";
+				function = "nand0";
+			};
+
 			mmc0_pins_a: mmc0@0 {
 				pins = "PF0", "PF1", "PF2",
 				       "PF3", "PF4", "PF5";
diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index 20d489cb2a..e0efcb3ba3 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -100,14 +100,10 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
 
 &mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
index 97b993f636..c8fd69f0a4 100644
--- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -125,15 +125,10 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
 
 &ir {
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
index 5113059098..78f6c24952 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
@@ -48,12 +48,8 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index caa1a6959c..d97fdacb35 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
@@ -55,6 +55,7 @@
 	aliases {
 		serial0 = &uart0;
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+		ethernet0 = &emac;
 		ethernet1 = &rtl8189;
 	};
 
@@ -110,14 +111,10 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
 
 &ir {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
index 8df5c74f04..adab1cbfc9 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts
@@ -53,6 +53,7 @@
 	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
 
 	aliases {
+		ethernet0 = &emac;
 		serial0 = &uart0;
 	};
 
@@ -95,14 +96,10 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
 
 &mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index b8340f74e7..afba264ea5 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
@@ -53,6 +53,7 @@
 	compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
 
 	aliases {
+		ethernet0 = &emac;
 		serial0 = &uart0;
 	};
 
@@ -167,12 +168,8 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&int_mii_phy>;
 	phy-mode = "mii";
-	allwinner,use-internal-phy;
 	allwinner,leds-active-low;
 	status = "okay";
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
 };
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
index e7079b26bc..136e4414a4 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
@@ -82,7 +82,13 @@
 	pinctrl-0 = <&emac_rgmii_pins>;
 	phy-supply = <&reg_gmac_3v3>;
 	phy-mode = "rgmii";
-	/delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
 };
 
 &mmc2 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
index f97b040b35..51aaf49b6d 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
@@ -69,8 +69,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_rgmii_pins>;
 	phy-supply = <&reg_gmac_3v3>;
+	phy-handle = <&ext_rgmii_phy>;
 	phy-mode = "rgmii";
-	/delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
 };
 
 &pio {
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index afa60793a2..d9d31fa3f5 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -144,9 +144,10 @@
 		#size-cells = <1>;
 		ranges;
 
-		syscon: syscon@01c00000 {
-			compatible = "allwinner,sun8i-h3-syscon","syscon";
-			reg = <0x01c00000 0x34>;
+		syscon: syscon@1c00000 {
+			compatible = "allwinner,sun8i-h3-system-controller",
+				     "syscon";
+			reg = <0x01c00000 0x1000>;
 		};
 
 		dma: dma-controller@01c02000 {
@@ -339,15 +340,12 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
-			emac_rgmii_pins: emac0@0 {
-				allwinner,pins = "PD0", "PD1", "PD2", "PD3",
-						"PD4", "PD5", "PD7",
-						"PD8", "PD9", "PD10",
-						"PD12", "PD13", "PD15",
-						"PD16", "PD17";
-				allwinner,function = "emac";
-				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			emac_rgmii_pins: emac0 {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+				       "PD5", "PD7", "PD8", "PD9", "PD10",
+				       "PD12", "PD13", "PD15", "PD16", "PD17";
+				function = "emac";
+				drive-strength = <40>;
 			};
 
 			mmc0_pins_a: mmc0@0 {
@@ -466,16 +464,51 @@
 
 		emac: ethernet@1c30000 {
 			compatible = "allwinner,sun8i-h3-emac";
-			reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
-			reg-names = "emac", "syscon";
+			syscon = <&syscon>;
+			reg = <0x01c30000 0x10000>;
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
-			reset-names = "ahb", "ephy";
-			clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
-			clock-names = "ahb", "ephy";
+			interrupt-names = "macirq";
+			resets = <&ccu RST_BUS_EMAC>;
+			reset-names = "stmmaceth";
+			clocks = <&ccu CLK_BUS_EMAC>;
+			clock-names = "stmmaceth";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+			};
+
+			mdio-mux {
+				compatible = "allwinner,sun8i-h3-mdio-mux";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mdio-parent-bus = <&mdio>;
+				/* Only one MDIO is usable at the time */
+				internal_mdio: mdio@1 {
+					compatible = "allwinner,sun8i-h3-mdio-internal";
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					int_mii_phy: ethernet-phy@1 {
+						compatible = "ethernet-phy-ieee802.3-c22";
+						reg = <1>;
+						clocks = <&ccu CLK_BUS_EPHY>;
+						resets = <&ccu RST_BUS_EPHY>;
+					};
+				};
+
+				external_mdio: mdio@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
 		};
 
 		gic: interrupt-controller@01c81000 {
diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
index dce688ec8e..72a8505d94 100644
--- a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
+++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
@@ -61,3 +61,17 @@
 	pinctrl-0 = <&uart0_pins_a>;
 	status = "okay";
 };
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-mode = "hw";
+	};
+};
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9597..d35aa479f7 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -192,6 +192,7 @@ struct sunxi_ccm_reg {
 #define ATB_DIV_1			0
 #define ATB_DIV_2			1
 #define ATB_DIV_4			2
+#define AHB_DIV_1			0
 #define CPU_CLK_SRC_OSC24M		1
 #define CPU_CLK_SRC_PLL1		2
 
@@ -317,6 +318,11 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_LCD0		3
 #endif
 
+#define CCM_NAND_CTRL_M(x)		((x) - 1)
+#define CCM_NAND_CTRL_N(x)		((x) << 16)
+#define CCM_NAND_CTRL_PLL6		(0x1 << 24)
+#define CCM_NAND_CTRL_ENABLE		(0x1 << 31)
+
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
 #define CCM_MMC_CTRL_N(x)		((x) << 16)