diff options
| author | Akshay Bhat <akshay.bhat@timesys.com> | 2016-07-29 11:44:46 -0400 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-09-06 18:22:48 +0200 |
| commit | ff3832205eb53b3e0ceebb6cd5d8891e0ec455d9 (patch) | |
| tree | 8f0a5fdb0535708720be9f8f923dcd0939631d2b /board/advantech/dms-ba16/clocks.cfg | |
| parent | 76b21efd555b9bc7e4e7fb8ebc7de2558403731a (diff) | |
| download | u-boot-ff3832205eb53b3e0ceebb6cd5d8891e0ec455d9.tar.gz | |
arm: imx: Add support for Advantech DMS-BA16 board
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
Diffstat (limited to 'board/advantech/dms-ba16/clocks.cfg')
| -rw-r--r-- | board/advantech/dms-ba16/clocks.cfg | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg new file mode 100644 index 0000000000..abc769c4e5 --- /dev/null +++ b/board/advantech/dms-ba16/clocks.cfg @@ -0,0 +1,25 @@ +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en 1 --> CKO1 enabled + * cko1_div 111 --> divide by 8 + * cko1_sel 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb |