diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2020-06-11 12:03:20 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-07 18:23:48 -0400 |
| commit | eb6211171d1349c43f3b0d0315f31605a0a67f2a (patch) | |
| tree | a3a72ba369135ab4ae00ca505c0f4809b73ab820 /board/armltd | |
| parent | 44a4042b01b547a100c387538196dacfa28b88f4 (diff) | |
| download | u-boot-eb6211171d1349c43f3b0d0315f31605a0a67f2a.tar.gz | |
arm: juno: Enable PCI
The ARM Juno boards in their -r1 and -r2 variants sport a PCIe
controller, which we configure already in board specific code to be ECAM
compliant. Hence we can just enable the generic ECAM driver to let
U-Boot use PCIe devices.
Add the respective options to the Juno defconfig to enable the PCI
framework and the generic ECAM driver, and initialise the driver upon
loading U-Boot.
Make some functions in the Juno PCIe init code static on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'board/armltd')
| -rw-r--r-- | board/armltd/vexpress64/pcie.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 02de58b360..733b190e59 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -72,9 +72,9 @@ JUNO_RESET_STATUS_PHY | \ JUNO_RESET_STATUS_RC) -void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, - unsigned long trsl_addr, int window_size, - int trsl_param) +static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, + unsigned long trsl_addr, int window_size, + int trsl_param) { /* X3PCI_ATR_SRC_ADDR_LOW: - bit 0: enable entry, @@ -94,7 +94,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, ((u64)1) << window_size, trsl_param); } -void xr3pci_setup_atr(void) +static void xr3pci_setup_atr(void) { /* setup PCIe to CPU address translation tables */ unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; @@ -141,7 +141,7 @@ void xr3pci_setup_atr(void) XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); } -void xr3pci_init(void) +static void xr3pci_init(void) { u32 val; int timeout = 200; @@ -193,5 +193,9 @@ void xr3pci_init(void) void vexpress64_pcie_init(void) { + /* Initialise and configure the PCIe host bridge. */ xr3pci_init(); + + /* Register the now ECAM complaint PCIe host controller with U-Boot. */ + pci_init(); } |