diff options
| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-09-27 13:09:07 +0000 |
|---|---|---|
| committer | Eugen Hristev <eugen.hristev@microchip.com> | 2019-10-08 09:16:11 +0300 |
| commit | 8ed15e4a3a0a1cfce08e97904887f7bd6c2fb27b (patch) | |
| tree | 6f7de364d9ad134f61176ffb341fc945cd4e6b9f /board/atmel | |
| parent | cd0fcf1965de9363c333a1f438aa4862f512aa84 (diff) | |
| download | u-boot-8ed15e4a3a0a1cfce08e97904887f7bd6c2fb27b.tar.gz | |
board: sam9x60ek: Add NAND flash support
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'board/atmel')
| -rw-r--r-- | board/atmel/sam9x60ek/sam9x60ek.c | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 62938741dd..e352afc67e 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -7,8 +7,10 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_sfr.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <debug_uart.h> @@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); +#ifdef CONFIG_CMD_NAND +static void sam9x60ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + unsigned int csa; + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); + + at91_periph_clk_enable(ATMEL_ID_PIOD); + + /* Enable CS3 */ + csa = readl(&sfr->ebicsa); + csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; + + writel(csa, &sfr->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), + &smc->cs[3].mode); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -48,6 +106,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_CMD_NAND + sam9x60ek_nand_hw_init(); +#endif return 0; } |