Merge git://git.denx.de/u-boot-fsl-qoriq

4 files changed, 131 insertions, 11 deletions

diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 354b864eb9..fc0c1f6f82 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -169,18 +169,64 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 
 	return 0;
 }
+#else
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+			       fixed_ddr_parm_0[i].ddr_settings,
+			       sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+		      strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t)2048 * 1024 * 1024;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	return ddr_size;
+}
 #endif
 
 int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 	puts("Initializing DDR....\n");
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+#else
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initialzing DDR using fixed setting\n");
+	dram_size = fixed_sdram();
+#else
+	gd->ram_size = 0x80000000;
+
+	return 0;
+#endif
+#endif
 	erratum_a008850_post();
 
 #ifdef CONFIG_FSL_DEEP_SLEEP
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index a77ddf3d24..6bc0eb67cc 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -45,4 +45,73 @@ static const struct board_specific_parameters *udimms[] = {
 	udimm0,
 };
 
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
+	.cs[0].bnds = 0x0000007F,
+	.cs[1].bnds = 0,
+	.cs[2].bnds = 0,
+	.cs[3].bnds = 0,
+	.cs[0].config = 0x80040322,
+	.cs[0].config_2 = 0,
+	.cs[1].config = 0,
+	.cs[1].config_2 = 0,
+	.cs[2].config = 0,
+	.cs[3].config = 0,
+	.timing_cfg_3 = 0x010C1000,
+	.timing_cfg_0 = 0x91550018,
+	.timing_cfg_1 = 0xBBB48C42,
+	.timing_cfg_2 = 0x0048C111,
+	.ddr_sdram_cfg = 0xC50C0008,
+	.ddr_sdram_cfg_2 = 0x00401100,
+	.ddr_sdram_cfg_3 = 0,
+	.ddr_sdram_mode = 0x03010210,
+	.ddr_sdram_mode_2 = 0,
+	.ddr_sdram_mode_3 = 0x00010210,
+	.ddr_sdram_mode_4 = 0,
+	.ddr_sdram_mode_5 = 0x00010210,
+	.ddr_sdram_mode_6 = 0,
+	.ddr_sdram_mode_7 = 0x00010210,
+	.ddr_sdram_mode_8 = 0,
+	.ddr_sdram_mode_9 = 0x00000500,
+	.ddr_sdram_mode_10 = 0x04000000,
+	.ddr_sdram_mode_11 = 0x00000400,
+	.ddr_sdram_mode_12 = 0x04000000,
+	.ddr_sdram_mode_13 = 0x00000400,
+	.ddr_sdram_mode_14 = 0x04000000,
+	.ddr_sdram_mode_15 = 0x00000400,
+	.ddr_sdram_mode_16 = 0x04000000,
+	.ddr_sdram_interval = 0x18600618,
+	.ddr_data_init = 0xDEADBEEF,
+	.ddr_sdram_clk_cntl = 0x03000000,
+	.ddr_init_addr = 0,
+	.ddr_init_ext_addr = 0,
+	.timing_cfg_4 = 0x00000002,
+	.timing_cfg_5 = 0x03401400,
+	.timing_cfg_6 = 0,
+	.timing_cfg_7 = 0x13300000,
+	.timing_cfg_8 = 0x02115600,
+	.timing_cfg_9 = 0,
+	.ddr_zq_cntl = 0x8A090705,
+	.ddr_wrlvl_cntl = 0x8675F607,
+	.ddr_wrlvl_cntl_2 = 0x07090800,
+	.ddr_wrlvl_cntl_3 = 0,
+	.ddr_sr_cntr = 0,
+	.ddr_sdram_rcw_1 = 0,
+	.ddr_sdram_rcw_2 = 0,
+	.ddr_cdr1 = 0x80040000,
+	.ddr_cdr2 = 0x0000A181,
+	.dq_map_0 = 0,
+	.dq_map_1 = 0,
+	.dq_map_2 = 0,
+	.dq_map_3 = 0,
+	.debug[28] = 0x00700046,
+
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{1550, 1650, &ddr_cfg_regs_1600},
+	{0, 0, NULL}
+};
+
+#endif
 #endif
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index c19f59a11c..de70aee867 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -14,14 +14,13 @@
 #include <fm_eth.h>
 #include <i2c.h>
 #include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 #include "../common/qixis.h"
 
 #include "ls1088a_qixis.h"
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
-
 #ifdef CONFIG_FSL_MC_ENET
 
 #define SFP_TX		0
@@ -612,7 +611,6 @@ static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
 int board_eth_init(bd_t *bis)
 {
 	int error = 0, i;
-	char *mc_boot_env_var;
 #ifdef CONFIG_FSL_MC_ENET
 	struct memac_mdio_info *memac_mdio0_info;
 	char *env_hwconfig = env_get("hwconfig");
@@ -655,9 +653,6 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
-	mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	error = cpu_eth_init(bis);
 
 	if (hwconfig_f("xqsgmii", env_hwconfig)) {
@@ -681,3 +676,10 @@ int board_eth_init(bd_t *bis)
 	error = pci_eth_init(bis);
 	return error;
 }
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 853d815da5..97accc90fd 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -15,15 +15,14 @@
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
-	char *mc_boot_env_var;
 	int i, interface;
 	struct memac_mdio_info mdio_info;
 	struct mii_dev *dev;
@@ -92,11 +91,15 @@ int board_eth_init(bd_t *bis)
 	dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 	wriop_set_mdio(WRIOP1_DPMAC2, dev);
 
-	mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 
 	return pci_eth_init(bis);
 }
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */