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authorStefano Babic <sbabic@denx.de>2015-07-10 09:21:44 +0200
committerStefano Babic <sbabic@denx.de>2015-07-10 09:21:44 +0200
commit1254ff97abb7606ccd0d7bdcd9f22581c50fe535 (patch)
tree61b31e61173154abd38aaa6584e84ea77314b861 /board/synopsys/axs101/axs101.c
parent54e0f96f764f662be186baae7d6c2c97423bc29d (diff)
parentf3edfd30541d6f245d7dfa6fa7354cc916cc53e1 (diff)
downloadu-boot-1254ff97abb7606ccd0d7bdcd9f22581c50fe535.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'board/synopsys/axs101/axs101.c')
-rw-r--r--board/synopsys/axs101/axs101.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 8c16410944..d4280f743a 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -56,3 +56,33 @@ int board_early_init_f(void)
return 0;
}
+
+#ifdef CONFIG_ISA_ARCV2
+#define RESET_VECTOR_ADDR 0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* All cores have reset vector pointing to 0 */
+ writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+ /* Make sure other cores see written value in memory */
+ flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START 0xF0001400
+
+/* Bits positions in CPU start CREG */
+#define BITS_START 0
+#define BITS_POLARITY 8
+#define BITS_CORE_SEL 9
+#define BITS_MULTICORE 12
+
+#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
+ (1 << BITS_POLARITY) | (1 << BITS_START)
+
+ writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif