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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 12:26:21 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 12:26:21 +0200 |
| commit | b1cdd8baa14f518288ceddb391d6587c1ecb3174 (patch) | |
| tree | c3d00b3193b2ee86b9679baf1933b10a7d07a13d /board/ti/dra7xx | |
| parent | 48b3ed217f58487c583d59575d7dfe2aafbb738d (diff) | |
| parent | 434f2cfcad9f70231ad5a096325ba72ef0d2a2cc (diff) | |
| download | u-boot-b1cdd8baa14f518288ceddb391d6587c1ecb3174.tar.gz | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'board/ti/dra7xx')
| -rw-r--r-- | board/ti/dra7xx/evm.c | 7 | ||||
| -rw-r--r-- | board/ti/dra7xx/mux_data.h | 12 |
2 files changed, 18 insertions, 1 deletions
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7f19655cfe..ae50d88c57 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -163,6 +163,8 @@ int spl_start_uboot(void) #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) +extern u32 *const omap_si_rev; + static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -189,7 +191,7 @@ static struct cpsw_platform_data cpsw_data = { .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, - .slaves = 1, + .slaves = 2, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, @@ -260,6 +262,9 @@ int board_eth_init(bd_t *bis) ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); + if (*omap_si_rev == DRA722_ES1_0) + cpsw_data.active_slave = 1; + ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index c9e202af68..7db70324e9 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -56,6 +56,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {RGMII0_RXD2, (IEN | M0) }, {RGMII0_RXD1, (IEN | M0) }, {RGMII0_RXD0, (IEN | M0) }, + {VIN2A_D12, (M3) }, + {VIN2A_D13, (M3) }, + {VIN2A_D14, (M3) }, + {VIN2A_D15, (M3) }, + {VIN2A_D16, (M3) }, + {VIN2A_D17, (M3) }, + {VIN2A_D18, (IEN | M3)}, + {VIN2A_D19, (IEN | M3)}, + {VIN2A_D20, (IEN | M3)}, + {VIN2A_D21, (IEN | M3)}, + {VIN2A_D22, (IEN | M3)}, + {VIN2A_D23, (IEN | M3)}, {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ |