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| author | Tom Rini <trini@konsulko.com> | 2019-05-26 14:45:25 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-26 14:45:25 -0400 |
| commit | 344a0e4367d0820b8eb2ea4a90132433e038095f (patch) | |
| tree | bf58156bdb467305dac74f175f5c81ef615d49ac /configs/mpc8308_p1m_defconfig | |
| parent | cc1e98b559e46630c3421a7762d02a58e5480926 (diff) | |
| download | u-boot-344a0e4367d0820b8eb2ea4a90132433e038095f.tar.gz | |
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'configs/mpc8308_p1m_defconfig')
| -rw-r--r-- | configs/mpc8308_p1m_defconfig | 55 |
1 files changed, 24 insertions, 31 deletions
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 0789ecd586..cb0da4701f 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -56,6 +56,28 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xFBFF8000 CONFIG_LBLAW2_NAME="CPLD" CONFIG_LBLAW2_LENGTH_32_KBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFC000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_64_MBYTES=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_SCY_4=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="SJA1000" +CONFIG_BR1_OR1_BASE=0xFBFF0000 +CONFIG_OR1_SCY_5=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="CPLD" +CONFIG_BR2_OR2_BASE=0xFBFF8000 +CONFIG_OR2_SCY_4=y +CONFIG_OR2_EHTR_1_CYCLE=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y @@ -71,6 +93,8 @@ CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 @@ -93,34 +117,3 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFC000000 -CONFIG_BR0_MACHINE_GPCM=y -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_64_MBYTES=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_SCY_4=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="SJA1000" -CONFIG_BR1_OR1_BASE=0xFBFF0000 -CONFIG_BR1_MACHINE_GPCM=y -CONFIG_BR1_PORTSIZE_8BIT=y -CONFIG_OR1_AM_32_KBYTES=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_EHTR_1_CYCLE=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="CPLD" -CONFIG_BR2_OR2_BASE=0xFBFF8000 -CONFIG_BR2_MACHINE_GPCM=y -CONFIG_BR2_PORTSIZE_8BIT=y -CONFIG_OR2_AM_32_KBYTES=y -CONFIG_OR2_SCY_4=y -CONFIG_OR2_EHTR_1_CYCLE=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y |