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| author | Breno Matheus Lima <breno.lima@nxp.com> | 2018-10-10 01:10:27 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-10-22 14:22:42 +0200 |
| commit | df11b0c4d4e3ca3821cf4cc6b13fb9fee1d5f891 (patch) | |
| tree | 76f814f419b104826b64620c0c603aa9b78c54b0 /doc/README.imx5 | |
| parent | 6d9b483f371836ec16d9ee4f85bea53eb05307ae (diff) | |
| download | u-boot-df11b0c4d4e3ca3821cf4cc6b13fb9fee1d5f891.tar.gz | |
doc: imx: reorganize i.MX documentation
Currently the U-Boot doc/ directory contains the following files
that are only relevant for i.MX devices:
- doc/README.imx25
- doc/README.imx27
- doc/README.imx5
- doc/README.imx6
- doc/README.imximage
- doc/README.mxc_hab
- doc/README.mxs
- doc/README.mxsimage
- doc/README.sdp
Move all content to a common i.MX folder for a better documentation
structure.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Diffstat (limited to 'doc/README.imx5')
| -rw-r--r-- | doc/README.imx5 | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/doc/README.imx5 b/doc/README.imx5 deleted file mode 100644 index ea0e144ced..0000000000 --- a/doc/README.imx5 +++ /dev/null @@ -1,40 +0,0 @@ -U-Boot for Freescale i.MX5x - -This file contains information for the port of U-Boot to the Freescale -i.MX5x SoCs. - -1. CONFIGURATION OPTIONS/SETTINGS ---------------------------------- - -1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. - This option should be enabled by all boards using the i.MX51 silicon - version up until (including) 3.0 running at 800MHz. - The PLL's in the i.MX51 processor can go out of lock due to a metastable - condition in an analog flip-flop when used at high frequencies. - This workaround implements an undocumented feature in the PLL (dither - mode), which causes the effect of this failure to be much lower (in terms - of frequency deviation), avoiding system failure, or at least decreasing - the likelihood of system failure. - -1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. - This option should be enabled for boards having a SYS_ON_OFF_CTL signal - connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the - reference designs. - -2. CONVENTIONS FOR FUSE ASSIGNMENTS ------------------------------------ - -2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the - natural MAC byte order (i.e. MSB first). - - This is an example how to program an example MAC address 01:23:45:67:89:ab - into the eFuses. Assure that the programming voltage is available and then - execute: - - => fuse prog -y 1 9 01 23 45 67 89 ab - - After programming a MAC address, consider locking the MAC fuses. This is - done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in - bank 1: - - => fuse prog -y 1 0 10 |