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| author | Janine Hagemann <j.hagemann@phytec.de> | 2018-08-28 08:25:39 +0200 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2018-10-10 12:28:54 -0500 |
| commit | 0f347a0096ad0c1e56d1b18b7eb60731d40d49c2 (patch) | |
| tree | a017c3bd38fb9918370d780e4103c288a7d7740a /doc | |
| parent | be71a74c59b7f34e83f3f6ea4b1a838de356c654 (diff) | |
| download | u-boot-0f347a0096ad0c1e56d1b18b7eb60731d40d49c2.tar.gz | |
net: phy: ti: Add binding for the CLK_OUT pin muxing
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/net/ti,dp83867.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt index f31c2da902..034146f5f8 100644 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -12,6 +12,8 @@ Required properties: compensate for the board being designed with the lanes swapped. - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the TX/RX lanes. + - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h + for applicable values Default child nodes are standard Ethernet PHY device nodes as described in doc/devicetree/bindings/net/ethernet.txt @@ -24,6 +26,7 @@ Example: ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; Datasheet can be found: |