Merge branch 'master' of git://git.denx.de/u-boot-sh

5 files changed, 386 insertions, 32 deletions

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index b5a6bcc3af..578e6a8049 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -74,6 +74,13 @@ config CLK_R8A77970
 	help
 	  Enable this to support the clocks on Renesas R8A77970 SoC.
 
+config CLK_R8A77990
+	bool "Renesas R8A77990 clock driver"
+	def_bool y if R8A77990
+	depends on CLK_RCAR_GEN3
+	help
+	  Enable this to support the clocks on Renesas R8A77990 SoC.
+
 config CLK_R8A77995
 	bool "Renesas R8A77995 clock driver"
 	def_bool y if R8A77995
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a65d89f59c..22a817a919 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
 obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 3a95647abe..99698b1f46 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -85,6 +85,28 @@ static const struct sd_div_table cpg_sd_div_table[] = {
 	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 };
 
+static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
+			       struct cpg_mssr_info *info, struct clk *parent)
+{
+	const struct cpg_core_clk *core;
+	int ret;
+
+	if (!renesas_clk_is_mod(clk)) {
+		ret = renesas_clk_get_core(clk, info, &core);
+		if (ret)
+			return ret;
+
+		if (core->type == CLK_TYPE_GEN3_PE) {
+			parent->dev = clk->dev;
+			parent->id = core->parent >> (priv->sscg ? 16 : 0);
+			parent->id &= 0xffff;
+			return 0;
+		}
+	}
+
+	return renesas_clk_get_parent(clk, info, parent);
+}
+
 static int gen3_clk_setup_sdif_div(struct clk *clk)
 {
 	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
@@ -93,7 +115,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
 	struct clk parent;
 	int ret;
 
-	ret = renesas_clk_get_parent(clk, info, &parent);
+	ret = gen3_clk_get_parent(priv, clk, info, &parent);
 	if (ret) {
 		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 		return ret;
@@ -134,7 +156,7 @@ static int gen3_clk_disable(struct clk *clk)
 	return renesas_clk_endisable(clk, priv->base, false);
 }
 
-static ulong gen3_clk_get_rate(struct clk *clk)
+static u64 gen3_clk_get_rate64(struct clk *clk)
 {
 	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 	struct cpg_mssr_info *info = priv->info;
@@ -142,20 +164,21 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 	const struct cpg_core_clk *core;
 	const struct rcar_gen3_cpg_pll_config *pll_config =
 					priv->cpg_pll_config;
-	u32 value, mult, prediv, postdiv, rate = 0;
+	u32 value, mult, div, prediv, postdiv;
+	u64 rate = 0;
 	int i, ret;
 
 	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 
-	ret = renesas_clk_get_parent(clk, info, &parent);
+	ret = gen3_clk_get_parent(priv, clk, info, &parent);
 	if (ret) {
 		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 		return ret;
 	}
 
 	if (renesas_clk_is_mod(clk)) {
-		rate = gen3_clk_get_rate(&parent);
-		debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent);
+		debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
 		      __func__, __LINE__, parent.id, rate);
 		return rate;
 	}
@@ -168,14 +191,14 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 	case CLK_TYPE_IN:
 		if (core->id == info->clk_extal_id) {
 			rate = clk_get_rate(&priv->clk_extal);
-			debug("%s[%i] EXTAL clk: rate=%u\n",
+			debug("%s[%i] EXTAL clk: rate=%llu\n",
 			      __func__, __LINE__, rate);
 			return rate;
 		}
 
 		if (core->id == info->clk_extalr_id) {
 			rate = clk_get_rate(&priv->clk_extalr);
-			debug("%s[%i] EXTALR clk: rate=%u\n",
+			debug("%s[%i] EXTALR clk: rate=%llu\n",
 			      __func__, __LINE__, rate);
 			return rate;
 		}
@@ -183,8 +206,8 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 		return -EINVAL;
 
 	case CLK_TYPE_GEN3_MAIN:
-		rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
-		debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
+		debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
 		      __func__, __LINE__,
 		      core->parent, pll_config->extal_div, rate);
 		return rate;
@@ -192,49 +215,61 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 	case CLK_TYPE_GEN3_PLL0:
 		value = readl(priv->base + CPG_PLL0CR);
 		mult = (((value >> 24) & 0x7f) + 1) * 2;
-		rate = gen3_clk_get_rate(&parent) * mult;
-		debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) * mult;
+		debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
 		      __func__, __LINE__, core->parent, mult, rate);
 		return rate;
 
 	case CLK_TYPE_GEN3_PLL1:
-		rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
-		debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
+		rate /= pll_config->pll1_div;
+		debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
 		      __func__, __LINE__,
-		      core->parent, pll_config->pll1_mult, rate);
+		      core->parent, pll_config->pll1_mult,
+		      pll_config->pll1_div, rate);
 		return rate;
 
 	case CLK_TYPE_GEN3_PLL2:
 		value = readl(priv->base + CPG_PLL2CR);
 		mult = (((value >> 24) & 0x7f) + 1) * 2;
-		rate = gen3_clk_get_rate(&parent) * mult;
-		debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) * mult;
+		debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
 		      __func__, __LINE__, core->parent, mult, rate);
 		return rate;
 
 	case CLK_TYPE_GEN3_PLL3:
-		rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
-		debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
+		rate /= pll_config->pll3_div;
+		debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
 		      __func__, __LINE__,
-		      core->parent, pll_config->pll3_mult, rate);
+		      core->parent, pll_config->pll3_mult,
+		      pll_config->pll3_div, rate);
 		return rate;
 
 	case CLK_TYPE_GEN3_PLL4:
 		value = readl(priv->base + CPG_PLL4CR);
 		mult = (((value >> 24) & 0x7f) + 1) * 2;
-		rate = gen3_clk_get_rate(&parent) * mult;
-		debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
+		rate = gen3_clk_get_rate64(&parent) * mult;
+		debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
 		      __func__, __LINE__, core->parent, mult, rate);
 		return rate;
 
 	case CLK_TYPE_FF:
-	case CLK_TYPE_GEN3_PE:		/* FIXME */
-		rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
-		debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+		rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
+		debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
 		      __func__, __LINE__,
 		      core->parent, core->mult, core->div, rate);
 		return rate;
 
+	case CLK_TYPE_GEN3_PE:
+		div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
+		rate = gen3_clk_get_rate64(&parent) / div;
+		debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
+		      __func__, __LINE__,
+		      (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
+		      div, rate);
+		return rate;
+
 	case CLK_TYPE_GEN3_SD:		/* FIXME */
 		value = readl(priv->base + core->offset);
 		value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
@@ -243,9 +278,9 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 			if (cpg_sd_div_table[i].val != value)
 				continue;
 
-			rate = gen3_clk_get_rate(&parent) /
+			rate = gen3_clk_get_rate64(&parent) /
 			       cpg_sd_div_table[i].div;
-			debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
+			debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
 			      __func__, __LINE__,
 			      core->parent, cpg_sd_div_table[i].div, rate);
 
@@ -255,7 +290,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 		return -EINVAL;
 
 	case CLK_TYPE_GEN3_RPC:
-		rate = gen3_clk_get_rate(&parent);
+		rate = gen3_clk_get_rate64(&parent);
 
 		value = readl(priv->base + core->offset);
 
@@ -272,7 +307,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 			  CPG_RPC_POSTDIV_MASK;
 		rate /= postdiv + 1;
 
-		debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
+		debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
 		      __func__, __LINE__,
 		      core->parent, prediv, postdiv, rate);
 
@@ -285,11 +320,16 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 	return -ENOENT;
 }
 
+static ulong gen3_clk_get_rate(struct clk *clk)
+{
+	return gen3_clk_get_rate64(clk);
+}
+
 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 {
 	/* Force correct SD-IF divider configuration if applicable */
 	gen3_clk_setup_sdif_div(clk);
-	return gen3_clk_get_rate(clk);
+	return gen3_clk_get_rate64(clk);
 }
 
 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
@@ -341,6 +381,8 @@ int gen3_clk_probe(struct udevice *dev)
 	if (!priv->cpg_pll_config->extal_div)
 		return -EINVAL;
 
+	priv->sscg = !(cpg_mode & BIT(12));
+
 	ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 0000000000..b3614a1355
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas R8A77990 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL3,
+	CLK_PLL0D4,
+	CLK_PLL0D6,
+	CLK_PLL0D8,
+	CLK_PLL0D20,
+	CLK_PLL0D24,
+	CLK_PLL1D2,
+	CLK_PE,
+	CLK_S0,
+	CLK_S1,
+	CLK_S2,
+	CLK_S3,
+	CLK_SDSRC,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77990_core_clks[] = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",     CLK_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
+	DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
+	DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
+
+	DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,	   1, 100),
+	DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),
+	DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),
+	DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),
+	DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),
+	DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
+	DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
+	DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D20,    1, 1),
+	DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
+	DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
+	DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
+	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
+	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
+
+	/* Core Clock Outputs */
+	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
+	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
+	DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
+	DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
+	DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
+	DEF_FIXED("s0d1",      R8A77990_CLK_S0D1,  CLK_S0,         1, 1),
+	DEF_FIXED("s0d3",      R8A77990_CLK_S0D3,  CLK_S0,         3, 1),
+	DEF_FIXED("s0d6",      R8A77990_CLK_S0D6,  CLK_S0,         6, 1),
+	DEF_FIXED("s0d12",     R8A77990_CLK_S0D12, CLK_S0,        12, 1),
+	DEF_FIXED("s0d24",     R8A77990_CLK_S0D24, CLK_S0,        24, 1),
+	DEF_FIXED("s1d1",      R8A77990_CLK_S1D1,  CLK_S1,         1, 1),
+	DEF_FIXED("s1d2",      R8A77990_CLK_S1D2,  CLK_S1,         2, 1),
+	DEF_FIXED("s1d4",      R8A77990_CLK_S1D4,  CLK_S1,         4, 1),
+	DEF_FIXED("s2d1",      R8A77990_CLK_S2D1,  CLK_S2,         1, 1),
+	DEF_FIXED("s2d2",      R8A77990_CLK_S2D2,  CLK_S2,         2, 1),
+	DEF_FIXED("s2d4",      R8A77990_CLK_S2D4,  CLK_S2,         4, 1),
+	DEF_FIXED("s3d1",      R8A77990_CLK_S3D1,  CLK_S3,         1, 1),
+	DEF_FIXED("s3d2",      R8A77990_CLK_S3D2,  CLK_S3,         2, 1),
+	DEF_FIXED("s3d4",      R8A77990_CLK_S3D4,  CLK_S3,         4, 1),
+
+	DEF_GEN3_SD("sd0",     R8A77990_CLK_SD0,   CLK_SDSRC,	  0x0074),
+	DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,	  0x0078),
+	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,	  0x026c),
+
+	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
+	DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
+	DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
+	DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),
+	DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),
+
+	DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
+	DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+	DEF_GEN3_PE("s3d2c",   R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+	DEF_GEN3_PE("s3d4c",   R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+	DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
+	DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
+	DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+	DEF_MOD("scif5",		 202,	R8A77990_CLK_S3D4C),
+	DEF_MOD("scif4",		 203,	R8A77990_CLK_S3D4C),
+	DEF_MOD("scif3",		 204,	R8A77990_CLK_S3D4C),
+	DEF_MOD("scif1",		 206,	R8A77990_CLK_S3D4C),
+	DEF_MOD("scif0",		 207,	R8A77990_CLK_S3D4C),
+	DEF_MOD("msiof3",		 208,	R8A77990_CLK_MSO),
+	DEF_MOD("msiof2",		 209,	R8A77990_CLK_MSO),
+	DEF_MOD("msiof1",		 210,	R8A77990_CLK_MSO),
+	DEF_MOD("msiof0",		 211,	R8A77990_CLK_MSO),
+	DEF_MOD("sys-dmac2",		 217,	R8A77990_CLK_S3D1),
+	DEF_MOD("sys-dmac1",		 218,	R8A77990_CLK_S3D1),
+	DEF_MOD("sys-dmac0",		 219,	R8A77990_CLK_S3D1),
+
+	DEF_MOD("cmt3",			 300,	R8A77990_CLK_R),
+	DEF_MOD("cmt2",			 301,	R8A77990_CLK_R),
+	DEF_MOD("cmt1",			 302,	R8A77990_CLK_R),
+	DEF_MOD("cmt0",			 303,	R8A77990_CLK_R),
+	DEF_MOD("scif2",		 310,	R8A77990_CLK_S3D4C),
+	DEF_MOD("sdif3",		 311,	R8A77990_CLK_SD3),
+	DEF_MOD("sdif1",		 313,	R8A77990_CLK_SD1),
+	DEF_MOD("sdif0",		 314,	R8A77990_CLK_SD0),
+	DEF_MOD("pcie0",		 319,	R8A77990_CLK_S3D1),
+	DEF_MOD("usb3-if0",		 328,	R8A77990_CLK_S3D1),
+	DEF_MOD("usb-dmac0",		 330,	R8A77990_CLK_S3D1),
+	DEF_MOD("usb-dmac1",		 331,	R8A77990_CLK_S3D1),
+
+	DEF_MOD("rwdt",			 402,	R8A77990_CLK_R),
+	DEF_MOD("intc-ex",		 407,	R8A77990_CLK_CP),
+	DEF_MOD("intc-ap",		 408,	R8A77990_CLK_S0D3),
+
+	DEF_MOD("audmac0",		 502,	R8A77990_CLK_S3D4),
+	DEF_MOD("drif7",		 508,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif6",		 509,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif5",		 510,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif4",		 511,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif3",		 512,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif2",		 513,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif1",		 514,	R8A77990_CLK_S3D2),
+	DEF_MOD("drif0",		 515,	R8A77990_CLK_S3D2),
+	DEF_MOD("hscif4",		 516,	R8A77990_CLK_S3D1C),
+	DEF_MOD("hscif3",		 517,	R8A77990_CLK_S3D1C),
+	DEF_MOD("hscif2",		 518,	R8A77990_CLK_S3D1C),
+	DEF_MOD("hscif1",		 519,	R8A77990_CLK_S3D1C),
+	DEF_MOD("hscif0",		 520,	R8A77990_CLK_S3D1C),
+	DEF_MOD("thermal",		 522,	R8A77990_CLK_CP),
+	DEF_MOD("pwm",			 523,	R8A77990_CLK_S3D4C),
+
+	DEF_MOD("fcpvd1",		 602,	R8A77990_CLK_S1D2),
+	DEF_MOD("fcpvd0",		 603,	R8A77990_CLK_S1D2),
+	DEF_MOD("fcpvb0",		 607,	R8A77990_CLK_S0D1),
+	DEF_MOD("fcpvi0",		 611,	R8A77990_CLK_S0D1),
+	DEF_MOD("fcpf0",		 615,	R8A77990_CLK_S0D1),
+	DEF_MOD("fcpcs",		 619,	R8A77990_CLK_S0D1),
+	DEF_MOD("vspd1",		 622,	R8A77990_CLK_S1D2),
+	DEF_MOD("vspd0",		 623,	R8A77990_CLK_S1D2),
+	DEF_MOD("vspb",			 626,	R8A77990_CLK_S0D1),
+	DEF_MOD("vspi0",		 631,	R8A77990_CLK_S0D1),
+
+	DEF_MOD("ehci0",		 703,	R8A77990_CLK_S3D4),
+	DEF_MOD("hsusb",		 704,	R8A77990_CLK_S3D4),
+	DEF_MOD("csi40",		 716,	R8A77990_CLK_CSI0),
+	DEF_MOD("du1",			 723,	R8A77990_CLK_S2D1),
+	DEF_MOD("du0",			 724,	R8A77990_CLK_S2D1),
+	DEF_MOD("lvds",			 727,	R8A77990_CLK_S2D1),
+
+	DEF_MOD("vin7",			 804,	R8A77990_CLK_S1D2),
+	DEF_MOD("vin6",			 805,	R8A77990_CLK_S1D2),
+	DEF_MOD("vin5",			 806,	R8A77990_CLK_S1D2),
+	DEF_MOD("vin4",			 807,	R8A77990_CLK_S1D2),
+	DEF_MOD("etheravb",		 812,	R8A77990_CLK_S3D2),
+
+	DEF_MOD("gpio6",		 906,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio5",		 907,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio4",		 908,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio3",		 909,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio2",		 910,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio1",		 911,	R8A77990_CLK_S3D4),
+	DEF_MOD("gpio0",		 912,	R8A77990_CLK_S3D4),
+	DEF_MOD("can-fd",		 914,	R8A77990_CLK_S3D2),
+	DEF_MOD("can-if1",		 915,	R8A77990_CLK_S3D4),
+	DEF_MOD("can-if0",		 916,	R8A77990_CLK_S3D4),
+	DEF_MOD("i2c6",			 918,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c5",			 919,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c-dvfs",		 926,	R8A77990_CLK_CP),
+	DEF_MOD("i2c4",			 927,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c3",			 928,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c2",			 929,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c1",			 930,	R8A77990_CLK_S3D2),
+	DEF_MOD("i2c0",			 931,	R8A77990_CLK_S3D2),
+
+	DEF_MOD("ssi-all",		1005,	R8A77990_CLK_S3D4),
+	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",		1017,	R8A77990_CLK_S3D4),
+	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
+ *--------------------------------------------------------------------
+ * 0		48 x 1		x100/4		x100/3		x100/3
+ * 1		48 x 1		x100/4		x100/3		 x58/3
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
+	{ 1,		100,	3,	100,	3,	},
+	{ 1,		100,	3,	 58,	3,	},
+};
+
+static const struct mstp_stop_table r8a77990_mstp_table[] = {
+	{ 0x00200000, 0x0, 0x00200000, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
+	{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+	{ 0x80000184, 0x180, 0x80000184, 0 },
+	{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
+	{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
+	{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+	{ 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a77990_get_pll_config(const u32 cpg_mode)
+{
+	return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a77990_cpg_mssr_info = {
+	.core_clk		= r8a77990_core_clks,
+	.core_clk_size		= ARRAY_SIZE(r8a77990_core_clks),
+	.mod_clk		= r8a77990_mod_clks,
+	.mod_clk_size		= ARRAY_SIZE(r8a77990_mod_clks),
+	.mstp_table		= r8a77990_mstp_table,
+	.mstp_table_size	= ARRAY_SIZE(r8a77990_mstp_table),
+	.reset_node		= "renesas,r8a77990-rst",
+	.mod_clk_base		= MOD_CLK_BASE,
+	.clk_extal_id		= CLK_EXTAL,
+	.clk_extalr_id		= ~0,
+	.get_pll_config		= r8a77990_get_pll_config,
+};
+
+static const struct udevice_id r8a77990_clk_ids[] = {
+	{
+		.compatible	= "renesas,r8a77990-cpg-mssr",
+		.data		= (ulong)&r8a77990_cpg_mssr_info
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(clk_r8a77990) = {
+	.name		= "clk_r8a77990",
+	.id		= UCLASS_CLK,
+	.of_match	= r8a77990_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+	.ops		= &gen3_clk_ops,
+	.probe		= gen3_clk_probe,
+	.remove		= gen3_clk_remove,
+};
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 2f410df42a..58e71f363c 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -31,8 +31,9 @@ enum rcar_gen3_clk_types {
 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
 		    _div_clean) \
-	DEF_BASE(_name, _id, CLK_TYPE_FF,			\
-		 (_parent_clean), .div = (_div_clean), 1)
+	DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,			\
+		 (_parent_sscg) << 16 | (_parent_clean),	\
+		 .div = (_div_sscg) << 16 | (_div_clean))
 
 struct rcar_gen3_cpg_pll_config {
 	u8 extal_div;
@@ -49,6 +50,7 @@ struct gen3_clk_priv {
 	struct cpg_mssr_info	*info;
 	struct clk		clk_extal;
 	struct clk		clk_extalr;
+	bool			sscg;
 	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 };