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authorJagan Teki <jagan@amarulasolutions.com>2020-05-24 22:13:15 +0530
committerKever Yang <kever.yang@rock-chips.com>2020-05-29 17:58:33 +0800
commit4648108c63d9d06cf882f8d216d5e3e13e272aea (patch)
tree9242e0fcc612fdf28dce34299f871a00f796b9f6 /drivers/clk
parent97de3935aabfe8632e6c737a9ecadabead802f04 (diff)
downloadu-boot-4648108c63d9d06cf882f8d216d5e3e13e272aea.tar.gz
clk: rk3399: Fix eMMC get_clk reg offset
Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 6a78837619..4caf3b5617 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -728,7 +728,7 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
div = 2;
break;
case SCLK_EMMC:
- con = readl(&cru->clksel_con[21]);
+ con = readl(&cru->clksel_con[22]);
div = 1;
break;
default: