diff options
| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:50 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:18 -0800 |
| commit | 03e664d8f4065010ccb6c75648192200a832fd8b (patch) | |
| tree | f0398fdcdc87e12da79a82cde310b1a11937641a /drivers/ddr/fsl/ddr2_dimm_params.c | |
| parent | b87e6f88e9218da3de371bb6cc8a34924153178e (diff) | |
| download | u-boot-03e664d8f4065010ccb6c75648192200a832fd8b.tar.gz | |
driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/ddr2_dimm_params.c')
| -rw-r--r-- | drivers/ddr/fsl/ddr2_dimm_params.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index d865df78a8..49cc1a07ff 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -211,10 +211,10 @@ compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) * * FIXME: use #define for the retvals */ -unsigned int -ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr2_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; @@ -310,8 +310,8 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); + pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( + get_memory_clk_period_ps(ctrl_num)); /* Compute timing parameters */ pdimm->trcd_ps = spd->trcd * 250; |