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| author | Faiz Abbas <faiz_abbas@ti.com> | 2019-06-11 00:43:40 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-17 11:12:08 -0400 |
| commit | d1c0a2200afb398f67a0c2c84948a079b44290a1 (patch) | |
| tree | 08b8e5f14b316139b4b7b8006aa7c7dcef4fdc43 /drivers/mmc/sdhci.c | |
| parent | 5a6098fff0b42aa1f48c02ee499dec1bcb625575 (diff) | |
| download | u-boot-d1c0a2200afb398f67a0c2c84948a079b44290a1.tar.gz | |
mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.
Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/mmc/sdhci.c')
| -rw-r--r-- | drivers/mmc/sdhci.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 61cf216e12..0a0770cc20 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -534,6 +534,34 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); } +void sdhci_set_uhs_timing(struct sdhci_host *host) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + + switch (mmc->selected_mode) { + case UHS_SDR50: + case MMC_HS_52: + reg |= SDHCI_CTRL_UHS_SDR50; + break; + case UHS_DDR50: + case MMC_DDR_52: + reg |= SDHCI_CTRL_UHS_DDR50; + break; + case UHS_SDR104: + case MMC_HS_200: + reg |= SDHCI_CTRL_UHS_SDR104; + break; + default: + reg |= SDHCI_CTRL_UHS_SDR12; + } + + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); +} + #ifdef CONFIG_DM_MMC static int sdhci_set_ios(struct udevice *dev) { |