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authorTom Rini <trini@konsulko.com>2019-10-25 20:07:24 -0400
committerTom Rini <trini@konsulko.com>2019-10-25 20:07:24 -0400
commitffc379b42c85466e1dd4c8fee8268801f26d2ab8 (patch)
treece8d48fcb69b088a1da5404dfef941907206f224 /drivers/mmc
parent15147dc6a96697880cf355ed9df127bd8c896f2c (diff)
parentec54c8c0001d151e9ba59410d35fe6a02fdcaf12 (diff)
downloadu-boot-ffc379b42c85466e1dd4c8fee8268801f26d2ab8.tar.gz
Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsWIP/25Oct2019
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/Kconfig2
-rw-r--r--drivers/mmc/mtk-sd.c29
2 files changed, 26 insertions, 5 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 18af0762a8..85fd1906bd 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -698,7 +698,7 @@ config FTSDC010_SDIO
config MMC_MTK
bool "MediaTek SD/MMC Card Interface support"
- depends on ARCH_MEDIATEK
+ depends on ARCH_MEDIATEK || ARCH_MTMIPS
depends on BLK && DM_MMC
depends on OF_CONTROL
help
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index f555357af2..ffd647fac7 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -217,6 +217,7 @@ struct mtk_sd_regs {
struct msdc_compatible {
u8 clk_div_bits;
+ u8 sclk_cycle_shift;
bool pad_tune0;
bool async_fifo;
bool data_tune;
@@ -269,6 +270,7 @@ struct msdc_host {
/* whether to use gpio detection or built-in hw detection */
bool builtin_cd;
+ bool cd_active_high;
/* card detection / write protection GPIOs */
#if CONFIG_IS_ENABLED(DM_GPIO)
@@ -664,7 +666,7 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
{
- u32 timeout, clk_ns;
+ u32 timeout, clk_ns, shift;
u32 mode = 0;
host->timeout_ns = ns;
@@ -673,10 +675,11 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
if (host->sclk == 0) {
timeout = 0;
} else {
+ shift = host->dev_comp->sclk_cycle_shift;
clk_ns = 1000000000UL / host->sclk;
timeout = (ns + clk_ns - 1) / clk_ns + clks;
/* unit is 1048576 sclk cycles */
- timeout = (timeout + (0x1 << 20) - 1) >> 20;
+ timeout = (timeout + (0x1 << shift) - 1) >> shift;
if (host->dev_comp->clk_div_bits == 8)
mode = (readl(&host->base->msdc_cfg) &
MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
@@ -850,7 +853,9 @@ static int msdc_ops_get_cd(struct udevice *dev)
if (host->builtin_cd) {
val = readl(&host->base->msdc_ps);
- return !(val & MSDC_PS_CDSTS);
+ val = !!(val & MSDC_PS_CDSTS);
+
+ return !val ^ host->cd_active_high;
}
#if CONFIG_IS_ENABLED(DM_GPIO)
@@ -1301,7 +1306,7 @@ static int msdc_drv_probe(struct udevice *dev)
host->mmc = &plat->mmc;
host->timeout_ns = 100000000;
- host->timeout_clks = 3 * 1048576;
+ host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
#ifdef CONFIG_PINCTRL
pinctrl_select_state(dev, "default");
@@ -1353,6 +1358,7 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
+ host->cd_active_high = dev_read_bool(dev, "cd-active-high");
return 0;
}
@@ -1374,8 +1380,20 @@ static const struct dm_mmc_ops msdc_ops = {
#endif
};
+static const struct msdc_compatible mt7620_compat = {
+ .clk_div_bits = 8,
+ .sclk_cycle_shift = 16,
+ .pad_tune0 = false,
+ .async_fifo = false,
+ .data_tune = false,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false
+};
+
static const struct msdc_compatible mt7623_compat = {
.clk_div_bits = 12,
+ .sclk_cycle_shift = 20,
.pad_tune0 = true,
.async_fifo = true,
.data_tune = true,
@@ -1386,6 +1404,7 @@ static const struct msdc_compatible mt7623_compat = {
static const struct msdc_compatible mt8516_compat = {
.clk_div_bits = 12,
+ .sclk_cycle_shift = 20,
.pad_tune0 = true,
.async_fifo = true,
.data_tune = true,
@@ -1395,6 +1414,7 @@ static const struct msdc_compatible mt8516_compat = {
static const struct msdc_compatible mt8183_compat = {
.clk_div_bits = 12,
+ .sclk_cycle_shift = 20,
.pad_tune0 = true,
.async_fifo = true,
.data_tune = true,
@@ -1403,6 +1423,7 @@ static const struct msdc_compatible mt8183_compat = {
};
static const struct udevice_id msdc_ids[] = {
+ { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },