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| author | Tom Rini <trini@konsulko.com> | 2021-03-12 08:00:39 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-03-12 08:00:39 -0500 |
| commit | ad7e1c7c6e2bde2b369f10984d41d6b1833453fb (patch) | |
| tree | f7bf2fcc1d49c12c45267a4dd9581983445c94d5 /drivers/pci/pci-aardvark.c | |
| parent | 4c8e9361bb3ced3b20e45ee94b3751da1a9ed850 (diff) | |
| parent | 15942805b7efe47e186d8b30ec378666561ad1f9 (diff) | |
| download | u-boot-WIP/12Mar2021.tar.gz | |
Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/12Mar2021
- Some more updates/sync's to A38x DDR3 code (Marek & Pali)
- marvell/ddr/AXP: Some type fixes found in the LTO work (Marek)
- Espressobin: Enable more options (Pali)
- pci-aardvark: Implement workaround for the readback value of
VEND_ID (Paili)
Diffstat (limited to 'drivers/pci/pci-aardvark.c')
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b4e1b60240..3b9309f52c 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -105,6 +105,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | |